ZYNQ Ultr FPGA Board AXU2CG-E User Manual
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103
B66_L12_P
C3
104
B66_L7_P
C1
105
B66_L12_N
C2
106
B66_L7_N
B1
107
GND
-
108
GND
-
109
B66_L13_N
D6
110
B66_L10_P
B4
111
B66_L13_P
D7
112
B66_L10_N
A4
113
GND
-
114
GND
-
115
B66_L8_N
A1
116
B66_L9_P
B3
117
B66_L8_P
A2
118
B66_L9_N
A3
119
GND
-
120
GND
-
Pin assignment of board to board connector J30
J30 Pin
Signal Name
Pin Number
J30 Pin
Signal Name
Pin Number
1
B66_L14_P
E5
2
FPGA_TDI
R18
3
B66_L14_N
D5
4
FPGA_TCK
R19
5
GND
-
6
GND
-
7
B66_L22_P
C8
8
FPGA_TDO
T21
9
B66_L22_N
B8
10
FPGA_TMS
N21
11
GND
-
12
GND
-
13
B66_L19_N
A5
14
B66_L21_N
A6
15
B66_L19_P
B5
16
B66_L21_P
A7
17
GND
-
18
GND
-
19
B66_L24_P
C9
20
B66_L17_P
F8
21
B66_L24_N
B9
22
B66_L17_N
E8
23
GND
-
24
GND
-
25
B66_L23_N
A8
26
B25_L9_P
C11
27
B66_L23_P
A9
28
B25_L9_N
B10
29
GND
-
30
GND
-
31
B25_L5_N
F10
32
B25_L10_P
B11
33
B25_L5_P
G11
34
B25_L10_N
A10
35
GND
-
36
GND
-
37
B66_L18_N
D9
38
B25_L12_P
D12