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Alinx ZYNQ AC7Z035, User Manual, Page: 3 / 33

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Summary of Contents for ZYNQ AC7Z035

Page 1: ...ZYNQ7000 FPGA Development Platform AC7Z035 System on Module...

Page 2: ...ZYNQ FPGA Development Board AC7Z035 User Manual 2 33 Amazon Store https www amazon com alinx Version Record Version Date Release By Description Rev 1 0 2020 06 24 Rachel Zhou First Release...

Page 3: ...cord 2 Part 1 AC7Z035 Core Board Introduction 4 Part 2 ZYNQ Chip 6 Part 3 DDR3 DRAM 9 Part 4 QSPI Flash 14 Part 5 eMMC Flash 16 Part 6 Clock Configuration 17 Part 7 LED Light 20 Part 8 Reset Circuit 2...

Page 4: ...L side can run at speeds up to 800MHz data rate 1600Mbps In addition two 256MBit QSPI FLASH and 8GB eMMC FLASH chips are integrated on the core board to boot the storage configuration and system files...

Page 5: ...ZYNQ FPGA Development Board AC7Z035 User Manual 5 33 Amazon Store https www amazon com alinx Figure 1 1 AC7Z035 Core Board Front View Figure 1 2 AC7Z035 Core Board Rear View...

Page 6: ...herals mainly include USB bus interface Ethernet interface SD SDIO interface I2C bus interface CAN bus interface UART interface GPIO etc The PS can operate independently and start up at power on or re...

Page 7: ...multi function IOs that can be configured as normal IO or peripheral control interfaces High bandwidth connection within PS and PS to PL The main parameters of the PL logic part are as follows Logic...

Page 8: ...FPGA Development Board AC7Z035 User Manual 8 33 Amazon Store https www amazon com alinx Figure 2 2 The Specific Chip Model Definition of ZYNQ7000 Series Figure 2 3 The XC7Z035 chip used on the Core B...

Page 9: ...interface of the BANK 502 of the ZYNQ Processing System PS The PL side DDR3 SDRAM has a maximum operating speed of 800MHz data rate 1600Mbps and two DDR3 memory systems are connected to the BANK33 an...

Page 10: ...igure 3 2 The Schematic Part of DDR3 DRAM on the PL side PS side DDR3 DRAM pin assignment Signal Name ZYNQ Pin Name ZYNQ Pin Number PS_DDR3_DQS0_P PS_DDR_DQS_P0_502 H24 PS_DDR3_DQS0_N PS_DDR_DQS_N0_50...

Page 11: ...R_DQ11_502 K23 PS_DDR3_D12 PS_DDR_DQ12_502 M25 PS_DDR3_D13 PS_DDR_DQ13_502 N24 PS_DDR3_D14 PS_DDR_DQ14_502 M24 PS_DDR3_D15 PS_DDR_DQ15_502 N23 PS_DDR3_D16 PS_DDR_DQ16_502 R26 PS_DDR3_D17 PS_DDR_DQ17_5...

Page 12: ..._A11 PS_DDR_A11_502 H21 PS_DDR3_A12 PS_DDR_A12_502 P20 PS_DDR3_A13 PS_DDR_A13_502 J20 PS_DDR3_A14 PS_DDR_A14_502 R20 PS_DDR3_BA0 PS_DDR_BA0_502 U22 PS_DDR3_BA1 PS_DDR_BA1_502 T22 PS_DDR3_BA2 PS_DDR_BA...

Page 13: ...1 PL_DDR3_D8 IO_L7N_T1_33 H1 PL_DDR3_D9 IO_L10N_T1_33 G1 PL_DDR3_D10 IO_L7P_T1_33 J1 PL_DDR3_D11 IO_L8N_T1_33 H3 PL_DDR3_D12 IO_L11N_T1_SRCC_33 K3 PL_DDR3_D13 IO_L8P_T1_33 H4 PL_DDR3_D14 IO_L11P_T1_SR...

Page 14: ...S_34 C9 PL_DDR3_A8 IO_L12N_T1_MRCC_34 F7 PL_DDR3_A9 IO_L18N_T2_34 A7 PL_DDR3_A10 IO_L24N_T3_34 A2 PL_DDR3_A11 IO_L11P_T1_SRCC_34 F8 PL_DDR3_A12 IO_L23N_T3_34 B1 PL_DDR3_A13 IO_L16P_T2_34 B10 PL_DDR3_A...

Page 15: ...e FPGA bit files ARM application code and other user data files The specific models and related parameters of QSPI FLASH are shown in Table 4 1 Position Model Capacity Factory U13 U14 W25Q256FVEI 256M...

Page 16: ...rts the JEDEC e MMC V5 0 standard HS MMC interface with level support of 1 8V or 3 3V The data width of the eMMC FLASH and ZYNQ connections is 4 bits Due to the large capacity and non volatile nature...

Page 17: ...Name ZYNQ Pin Name ZYNQ Pin Number MMC_CCLK PS_MIO48_501 B21 MMC_CMD PS_MIO47_501 B19 MMC_D0 PS_MIO46_501 E17 MMC_D1 PS_MIO49_501 A18 MMC_D2 PS_MIO50_501 B22 MMC_D3 PS_MIO51_501 B20 Part 6 Clock Conf...

Page 18: ...FPGA core board AC7Z035 The input of the clock is connected to the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip The schematic diagram is shown in Figure 2 6 2 Figure 6 2 Active crystal oscill...

Page 19: ...GA BANK34 which can be used to drive the DDR3 controller and user logic in the FPGA The schematic diagram of the clock source is shown in Figure 6 3 Figure 6 3 PL system clock source PL Clock pin assi...

Page 20: ...GA core board one of which is the power indicator light PWR one is the configuration LED light DONE and one is the user LED light When the core board is powered the power indicator will illuminate whe...

Page 21: ...reset circuit on the AC7Z035 core board The reset input signal is connected to the reset button on the carrier board The reset output is connected to the PS reset pin of the ZYNQ chip The user can use...

Page 22: ...rt 9 Power Supply The AC7Z035 FPGA core board is powered by DC5V and is powered by a connection carrier board The power supply design diagram on the FPGA board is shown in Figure 9 1 Figure 9 1 Power...

Page 23: ...the LDO chip The functions of each power distribution are shown in the following table Power Supply Function 1 0V ZYNQ PS and PL section Core Voltage 1 8V ZYNQ PS and PL partial auxiliary voltage BANK...

Page 24: ...pment Board AC7Z035 User Manual 24 33 Amazon Store https www amazon com alinx Figure 9 2 Power Supply on the AX7Z035 Core Board Part 10 AC7Z035 Core Board Size Dimension Figure 10 1 AC7Z035 Core Board...

Page 25: ...onnects JTAG and BANK35 IO 1 8V level standard J32 connects PS MIO BANK13 IO and 5V power supply Pin assignment of J29 connector J29 Pin Signal Name ZYNQ Pin Number J29 Pin Signal Name ZYNQ Pin Number...

Page 26: ...F15 57 B12_L15_N AD15 58 B12_L16_N AF14 59 GND 60 GND 61 B12_L14_P AB15 62 B12_L13_N AD14 63 B12_L14_N AB14 64 B12_L13_P AC14 65 GND 66 GND 67 B12_L10_N AF13 68 B12_L19_P Y17 69 B12_L10_P AE13 70 B12_...

Page 27: ...B12_L6_P AA13 110 B12_L9_P AE11 111 B12_L6_N AA12 112 B12_L9_N AF10 113 GND 114 GND 115 B12_L1_P Y12 116 B12_L2_P AB12 117 B12_L1_N Y11 118 B12_L2_N AC11 119 GND 120 GND Pin assignment of J30 connect...

Page 28: ...50 BANK112_RX3_N T3 51 BANK112_TX3_P R2 52 BANK112_RX3_P T4 53 GND R13 54 GND R13 55 BANK112_CLK0_N R5 56 BANK112_CLK1_N U5 57 BANK112_CLK0_P R6 58 BANK112_CLK1_P U6 59 GND 60 GND R13 61 62 BANK111_R...

Page 29: ...17 118 119 GND 120 GND Pin assignment of J31 connector J31 Pin Signal Name ZYNQ Pin Number J31 Pin Signal Name ZYNQ Pin Number 1 FPGA_TCK W12 2 FPGA_TDI V11 3 FPGA_TMS W11 4 FPGA_TDO W10 5 GND 6 GND 7...

Page 30: ...46 B35_L19_P D13 47 GND 48 GND 49 B35_L1_N E12 50 B35_L21_N A14 51 B35_L1_P F12 52 B35_L21_P A15 53 GND 54 GND 55 B35_L17_N B15 56 B35_L14_P F15 57 B35_L17_P B16 58 B35_L14_N E15 59 GND 60 GND 61 B35...

Page 31: ...D 120 GND Pin assignment of J32 connector J32 Pin Signal Name ZYNQ Pin Number J32 Pin Signal Name ZYNQ Pin Number 1 PS_MIO5 C26 2 PS_MIO17 G17 3 PS_MIO4 F24 4 PS_MIO18 G20 5 GND 6 GND 7 PS_MIO14 D23 8...

Page 32: ...K19 39 PS_MIO45 C18 40 PS_MIO29 E20 41 GND 42 GND 43 44 PS_MIO36 K16 45 46 PS_MIO31 E21 47 GND 48 GND 49 50 PS_MIO32 K17 51 52 PS_MIO33 E22 53 GND 54 GND 55 56 PS_MIO34 J16 57 58 PS_MIO35 D19 59 GND 6...

Page 33: ...3_L4_P AD25 93 B13_L6_N AB24 94 B13_L4_N AD26 95 GND 96 GND 97 B13_L2_N AC26 98 B13_L5_P AF24 99 B13_L2_P AB26 100 B13_L5_N AF25 101 GND 102 GND 103 B13_L12_P AC23 104 B13_L3_P AE25 105 B13_L12_N AC24...

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