ZYNQ FPGA Development Board AC7Z035 User Manual
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Figure 6-1: Clock source in the Core Board
PS system clock source
The ZYNQ chip provides a 33.333MHz clock input to the PS section via
the X4 crystal on the FPGA core board AC7Z035. The input of the clock is
connected to the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip.
The schematic diagram is shown in Figure 2-6-2:
Figure 6-2: Active crystal oscillator to the PS section
PS Clock Pin Assignment
Signal Name
ZYNQ Pin
PS_CLK
B24
BANK
500
ZYNQ
Single-ended Clock
33.33 Mhz
BANK
34
Differential Clock
200 Mhz
BANK
111
Differential Clock
200 Mhz
PS_CLCK
PS_CLCK_P
PS_CLCK_N
Bank111_CLK1_P
Bank111_CLK1_N