ZYNQ FPGA Development Board AC7Z035 User Manual
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the DCDC chip TPS82084 and TPS82085 to generate four power supplies:
+1.5V, +3.3V, MGT_1.5V and +1.5V. The MGT_1.5V power supply generates
+1.0V and +1.2V power supplies for GTX through two LDO chips TPS74401,
and +3.3V generates GTX auxiliary power +1.8V through an LDO chip
SPX3819-1-8. The VTT and VREF voltages of the DDR3 of the PS section and
the PL section are generated by U6, U9. In addition, the IO power supply of
BANK12 and BANK13 is generated by two SPX3819M5-3-3. Users can
change the IO input and output of these two BANKs to other voltage standards
by replacing the LDO chip.
The functions of each power distribution are shown in the following table:
：
Power Supply
Function
+1.0V
ZYNQ PS and PL section Core Voltage
+1.8V
ZYNQ PS and PL partial auxiliary voltage,BANK501, BANK35, eMMC
+3.3V
ZYNQ Bank0,Bank500
，
QSIP FLASH, Clock Crystal
+1.5V
DDR3, ZYNQ Bank501, Bank33,Bank34,
VCCIO12
ZYNQ Bank12
VCCIO13
ZYNQ Bank13
VREF,VTT(+0.75V)
PS DDR3
，
PL DDR3
M1.0V)
ZYNQ Bank111, Bank112
M1.2V)
ZYNQ Bank111, Bank112
MGT1.8V)
ZYNQ Bank111, Bank112
Because the power supply of the ZYNQ FPGA has the power-on
sequence requirements, in the circuit design, we have designed according to
the power requirements of the chip. The power-on sequence is
+1.0V->+1.8V->(+1.5 V, +3.3V, VCCIO12,VCCIO13) circuit design to ensure
the normal operation of the chip.
The physical diagram of the power circuit on the AX7Z035 core board is
shown in Figure 9-2: