ZYNQ Ultr FPGA Board AXU7EV User Manual
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MIPI interface pin assignment
Signal Name
ZYNQ Pin Name
ZYNQ
Pin
Number
Description
MIPI_CLK_N
B65_L1_N
AP20
MIPI Input Clock Positive
MIPI_CLK_P
B65_L1_P
AP19
MIPI Input Clock Negative
MIPI_LAN0_N
B65_L2_N
AN19
MIPI Input Date LANE0 Negative
MIPI_LAN0_P
B65_L2_P
AM19
MIPI Input Date LANE0 Positive
MIPI_LAN1_N
B65_L3_N
AP22
MIPI Input Date LANE1 Negative
MIPI_LAN1_P
B65_3_P
AP21
MIPI Input Date LANE1 Positive
CAM_GPIO
B87_L5_N
M8
GPIO Control of Camera
CAM_CLK
B87_L5_P
M9
Clock Input of Camera
CAM_SCL
B87_L11_P
H7
I2C Clock of Camera
CAM_SDA
B87_L11_N
G7
I2C Data of Camera
Part 3.13: FMC Interface
The AXU7EV FPGA Carrier board has a standard FMC LPC expansion
port that can be connected to various FMC modules of XILINX or ALINX (HDMI
input and output modules, binocular camera modules, high-speed AD modules,
etc.). The FMC expansion port contains 36 pairs of differential IO signals and 8
pairs of GTX Transceivers.
The 36 pairs of differential signals of the FMC expansion port are
connected to the IO of the BANK28 and BANK64 of the ZYNQ Ult chip.
The level standard is 1.8V, and the differential signal supports LVDS data
communication, 2 pairs of GTX transceiver signals are connected to BANK225.
The schematic diagram of ZYNQ Ult and FMC connectors is shown in
Figure 3-13-1.