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Alinx AXU7EV User Manual Download Page 30

ZYNQ Ultr FPGA Board AXU7EV User Manual

30 / 68

Amazon Store: https://www.amazon.com/alinx

Part 2.8: ACU7EV Core Board Size Dimension

Figure 2-8-1: ACU7EV Core Board Size Dimension

Part 2.9: Board to Board Connectors pin assignment

The core board has a total of four high-speed expansion ports. It uses four

120-pin inter-board connectors (J29/J30/J31/J32) to connect to the carrier
board. The connectors used is Panasonic AXK5A2137YG, and the
corresponding connector model in the carrier board is Panasonic
AXK6A2337YG.

J29 connector

J29 connects to +12V power supply, the IO of BANK28, BANK87,BANK88.

the level standard of BANK87, 88 is 3.3V, the level standard of BANK28 is 1.8V,
The Level of PS MIO is +1.8V.

Pin assignment of board to board connector J29

Summary of Contents for AXU7EV

Page 1: ...ZYNQ UltraScale FPGA Development Board AXU7EV User Manual...

Page 2: ...ZYNQ Ultrascale FPGA Board AXU7EV User Manual 2 68 Amazon Store https www amazon com alinx Version Record Version Date Release By Description Rev 1 1 2021 07 28 Rachel Zhou First Release...

Page 3: ...r Supply 28 Part 2 8 ACU7EV Core Board Size Dimension 30 Part 2 9 Board to Board Connectors pin assignment 30 Part 3 Carrier Board 39 Part 3 1 Carrier Board Introduction 39 Part 3 2 PCIe Slot 39 Part...

Page 4: ...mmunication Interface 60 Part 3 16 JTAG Debug Port 61 Part 3 17 Real time Clock 62 Part 3 18 EEPROM and Temperature Sensor 63 Part 3 19 User LEDs 64 Part 3 20 Keys 65 Part 3 21 DIP Switch Configuratio...

Page 5: ...side of the core board has 4 pieces of 1GB DDR4 SDRAM chip In the design of carrier board we have extended a wealth of interfaces for users such as 1 FMC LPC interface 1 M 2 SSD interface 1 Mini DP i...

Page 6: ...On the PS side and PL side of the ZU7EV chip there are 4 DDR4 and 4 DDR4 respectively each with a capacity of up to 1GB which enables the ARM system and FPGA system to independently process and store...

Page 7: ...consists of ZU7EV 4GB DDR4 PS 4GB DDR4 PL 8GB eMMC FLASH 512Mb QSPI FLASH and there are 2 crystal oscillators to provide the clock a single ended 33 3333MHz crystal oscillator for the PS system and a...

Page 8: ...ip from TI supports up to 4K 60Hz output HDMI Input Interface 1 HDMI video input interface using TMDS181IRGZT HDMI decoding chip from TI supports up to 4K 60Hz input and supports data input in differe...

Page 9: ...s 4Pin green terminal blocks 485 Communication Interface Two way 485 communication interface using MAX3485 chip of MAXIM company The interface uses 6Pin green terminal blocks MIPI Interface 2 Lane MIP...

Page 10: ...nment around the FPGA development board EEPROM One EEPROM 24LC04 with I2C interface Real Time Clock RTC 1 built in RTC real time clock LED Lights 5 LEDs include 1 LED on the core board 4 LEDs on the c...

Page 11: ...z data rate 2400Mbps and the highest operating speed of DDR4 SDRAM on the PL side can reach 1200MHz data rate 2400Mbps In addition two 256MBit QSPI FLASH and an 8GB eMMC FLASH chip are also integrated...

Page 12: ...th a speed of up to 1 3Ghz and supports Level 2 Cache it also contains 2 Cortex R5 processors with a speed of up to 533Mhz The ZU7EV chip supports 32 bit or 64 bit DDR4 LPDDR4 DDR3 DDR3L LPDDR3 memory...

Page 13: ...uad core Cortex A53 processor speed up to 1 3GHz each CPU 32KB level 1 instruction and data cache 1MB level 2 cache shared by 2 CPUs ARM dual core Cortex R5 processor speed up to 533MHz each CPU 32KB...

Page 14: ...ES and SHA System monitoring 10 bit 1Mbps AD sampling for temperature and voltage detection The main parameters of the PL logic part are as follows Logic Cells 504K CLB Flip flops 460 8K Look up table...

Page 15: ...GA The specific configuration of DDR4 SDRAM is shown in Table 2 3 1 below Position Bit Number Chip Model Capacity Factory PS U4 U5 U6 U7 MT40A512M16LY 062E 512M x 16bit Micron PL U17 U19 U45 U46 MT40A...

Page 16: ...0_504 AN27 PS_DDR4_DQS0_P PS_DDR_DQS_P0_504 AN26 PS_DDR4_DQS1_N PS_DDR_DQS_N1_504 AP30 PS_DDR4_DQS1_P PS_DDR_DQS_P1_504 AN29 PS_DDR4_DQS2_N PS_DDR_DQS_N2_504 AJ26 PS_DDR4_DQS2_P PS_DDR_DQS_P2_504 AH26...

Page 17: ...28 PS_DDR4_DQ12 PS_DDR_DQ12_504 AM31 PS_DDR4_DQ13 PS_DDR_DQ13_504 AP31 PS_DDR4_DQ14 PS_DDR_DQ14_504 AN31 PS_DDR4_DQ15 PS_DDR_DQ15_504 AM30 PS_DDR4_DQ16 PS_DDR_DQ16_504 AF25 PS_DDR4_DQ17 PS_DDR_DQ17_50...

Page 18: ..._DDR_DQ47_504 V27 PS_DDR4_DQ48 PS_DDR_DQ48_504 AA32 PS_DDR4_DQ49 PS_DDR_DQ49_504 AA33 PS_DDR4_DQ50 PS_DDR_DQ50_504 AA34 PS_DDR4_DQ51 PS_DDR_DQ51_504 AE34 PS_DDR4_DQ52 PS_DDR_DQ52_504 AD34 PS_DDR4_DQ53...

Page 19: ...R4_A8 PS_DDR_A8_504 AJ31 PS_DDR4_A9 PS_DDR_A9_504 AH31 PS_DDR4_A10 PS_DDR_A10_504 AG31 PS_DDR4_A11 PS_DDR_A11_504 AF31 PS_DDR4_A12 PS_DDR_A12_504 AG30 PS_DDR4_A13 PS_DDR_A13_504 AF30 PS_DDR4_ODT0 PS_D...

Page 20: ...QS7_N IO_L4N_T0U_N7_DBC_AD7N_68 J11 PL_DDR4_DQS7_P IO_L4P_T0U_N6_DBC_AD7P_68 K12 PL_DDR4_DQ0 IO_L9N_T1L_N5_AD12N_67 E17 PL_DDR4_DQ1 IO_L11P_T1U_N8_GC_67 D15 PL_DDR4_DQ2 IO_L8P_T1L_N2_AD5P_67 D17 PL_DD...

Page 21: ...DDR4_DQ35 IO_L14P_T2L_N2_GC_68 F11 PL_DDR4_DQ36 IO_L18P_T2U_N10_AD2P_68 D12 PL_DDR4_DQ37 IO_L15N_T2L_N5_AD11N_68 H12 PL_DDR4_DQ38 IO_L15P_T2L_N4_AD11P_68 H13 PL_DDR4_DQ39 IO_L14N_T2L_N3_GC_68 E10 PL_D...

Page 22: ...P_T0L_N0_DBC_68 M13 PL_DDR4_A0 IO_L10P_T1U_N6_QBC_AD4P_66 AK8 PL_DDR4_A1 IO_L6P_T0U_N10_AD6P_66 AM9 PL_DDR4_A2 IO_L10N_T1U_N7_QBC_AD4N_66 AL8 PL_DDR4_A3 IO_L5N_T0U_N9_AD14N_66 AM10 PL_DDR4_A4 IO_L11N_...

Page 23: ...EW9 which uses the 1 8V CMOS voltage standard Due to the non volatile nature of QSPI FLASH it can be used as a boot device for the system to store the boot image of the system These images mainly incl...

Page 24: ...1_QSPI0_IO1 PS_MIO1_500 C24 MIO2_QSPI0_IO2 PS_MIO2_500 B24 MIO3_QSPI0_IO3 PS_MIO3_500 E25 MIO4_QSPI0_IO0 PS_MIO4_500 A25 MIO5_QSPI0_SS_B PS_MIO5_500 D25 MIO10_QSPI1_IO2 PS_MIO10_500 F26 MIO11_QSPI1_IO...

Page 25: ...iles and other user data files The specific models and related parameters of eMMC FLASH are shown in Table 2 5 1 Position Model Capacity Factory U19 MTFC8GAKAJCN 4M 8G Byte Micron Table 2 5 1 eMMC FLA...

Page 26: ...iguration The core board provides reference clock and RTC real time clock for PS system and PL logic respectively so that PS system and PL logic can work independently The schematic diagram of the clo...

Page 27: ...ssignment Signal Name Pin PS_PADI_503 M25 PS_PADO_503 L25 PS System Clock Source The X1 crystal on the core board provides a 33 333MHz clock input for the PS part The clock input is connected to the P...

Page 28: ...clock source is shown in Figure 2 6 4 Figure 2 6 4 PL system clock source Clock pin assignment Signal Name Pin PL_CLK0_P AJ9 PL_CLK0_N AK9 Part 2 7 Power Supply The power supply voltage of the ACU7EV...

Page 29: ...ZYNQ Ultrascale FPGA Board AXU7EV User Manual 29 68 Amazon Store https www amazon com alinx...

Page 30: ...peed expansion ports It uses four 120 pin inter board connectors J29 J30 J31 J32 to connect to the carrier board The connectors used is Panasonic AXK5A2137YG and the corresponding connector model in t...

Page 31: ...B88_L3_N A2 27 B88_L8_P E4 28 B88_L3_P A3 29 GND 30 GND 31 B88_L7_N B4 32 B88_L6_N B3 33 B88_L7_P C4 34 B88_L6_P C3 35 B88_L9_N F4 36 B88_L10_N A5 37 B88_L9_P F5 38 B88_L10_P B5 39 GND 40 GND 41 B88_...

Page 32: ...B28_L23_P A22 98 B28_L17_P D22 99 GND 100 GND 101 PS_MIO43 E30 102 103 PS_MIO26 A29 104 PS_MIO32 B31 105 PS_MIO27 A30 106 PS_MIO35 C31 107 PS_MIO31 B30 108 PS_MIO36 C32 109 PS_MIO40 D31 110 PS_MIO37 C...

Page 33: ...USB_DATA0 G34 33 34 USB_DATA1 H29 35 GND 36 GND 37 B28_L18_N G26 38 USB_DATA2 G31 39 B28_L18_P G25 40 USB_DATA3 H32 41 B28_L14_N G24 42 USB_DATA4 H33 43 B28_L14_P G23 44 USB_DATA5 H34 45 GND 46 GND 47...

Page 34: ...34 106 505_TX0_N U30 107 505_RX0_P U33 108 505_TX0_P U29 109 GND 110 GND 111 505_CLK0_N T28 112 505_CLK1_N P28 113 505_CLK0_P T27 114 505_CLK1_P P27 115 GND 116 GND 117 505_CLK2_N M28 118 505_CLK3_N M...

Page 35: ...0 44 B65_L4_N AN21 45 B65_L15_P AG19 46 B65_L4_P AM21 47 B65_L20_N AC19 48 B65_L11_N AK20 49 B65_L20_P AB19 50 B65_L11_P AJ20 51 GND 52 GND 53 B65_L23_N AD19 54 B65_L1_N AP20 55 B65_L23_P AC18 56 B65_...

Page 36: ...AD15 115 B64_L22_N AA15 116 B64_L19_N AE15 117 B64_L13_P AH18 118 B64_L23_P AA14 119 B64_L13_N AH17 120 B64_L23_N AB14 Pin assignment of board to board connector J32 J32 connects to the the transceiv...

Page 37: ...56 224_CLK0_P AB8 57 224_CLK1_N AA9 58 224_CLK0_N AB7 59 GND 60 GND 61 225_CLK1_P W10 62 225_CLK0_P Y8 63 225_CLK1_N W9 64 225_CLK0_N Y7 65 GND 66 GND 67 225_RX1_P AB4 68 225_RX0_P AC2 69 225_RX1_N A...

Page 38: ...ww amazon com alinx 103 226_RX2_P R2 104 226_TX2_P R6 105 226_RX2_N R1 106 226_TX2_N R5 107 GND 108 GND 109 226_RX1_P U2 110 226_TX1_P T4 111 226_RX1_N U1 112 226_TX1_N T3 113 GND 114 GND 115 226_RX0_...

Page 39: ...1 Channel HDMI video input interface 2 Channel 10 100M 1000M Ethernet RJ 45 interface 2 Channel USB Uart Interfaces 2 SFP Interface 1 Channel Micro SD card slot 1 Channel MIPI camera interface 1 Chann...

Page 40: ...h as 8G bit bandwidth The PCIe interface schematic is shown in Figure 3 2 1 below where the TX signal is connected in AC coupling mode Figure 3 2 1 PCIe Interface Schematic PCIe x8 Interface FPGA Pin...

Page 41: ...223_TX0_P AN6 PCIE Channel 0 Data Receive Positive PCIE_TX1_N 223_TX1_N AM3 PCIE Channel 1 Data Receive Negative PCIE_TX1_P 223_TX1_P AM4 PCIE Channel 1 Data Receive Positive PCIE_TX2_N 223_TX2_N AL5...

Page 42: ...is directly connected to the BANK505 PS MGT transceiver of ZU7EV and the TX signal and RX signal of one channel are connected to the LANE1 of MGT in a differential signal mode The PCIE clock is provi...

Page 43: ...The interface supports VESA DisplayPort V1 2a output standard up to 4K x 2K 30Fps output supports Y only YCbCr444 YCbCr422 YCbCr420 and RGB video formats each color supports 6 8 10 or 12 bits The Disp...

Page 44: ...PS_MIO27 A30 DP Auxiliary Data Output DP_AUX_IN_MIO30 PS_MIO30 A33 DP Auxiliary Data Input DP_OE_MIO29 PS_MIO29 A32 DP Auxiliary Data Output Enable DP_HPD_MIO28 PS_MIO28 A31 DP Insertion Signal Detect...

Page 45: ...1_P T31 USB3 0 Data Receive Negative USB_DATA0 USB_DATA0 G34 USB2 0 Data Bit0 USB_DATA1 USB_DATA1 H29 USB2 0 Data Bit1 USB_DATA2 USB_DATA2 G31 USB2 0 Data Bit2 USB_DATA3 USB_DATA3 H32 USB2 0 Data Bit3...

Page 46: ...interface supports up to 4K 60Hz output The HDMI video output data is connected to the BANK226 GTH transceiver the clock is connected to BANK64 and the remaining auxiliary channels are connected to B...

Page 47: ...HDMI_TX0_DDC_SDA B88_L1_P E1 TMDS Bidirectional DDC Data HDMI_TX0_HPD B88_L1_N D1 Hot Plug Detection HDMI_TX0_OUT_OE B88_L4_P E3 Operation Enable Pin Part 3 7 HDMI Input Interface There is 1 HDMI inp...

Page 48: ...n Name FPGA Pin Numb er Description HDMI_IN0_RX_0N 226_RX0_N V3 HDMI Video Input Signal Data 0 Negative HDMI_IN0_RX_0P 226_RX0_P V4 HDMI Video Input Signal Data 0 Positive HDMI_IN0_RX_1N 226_RX1_N U1...

Page 49: ...g Signal 8T49N241_LOL B88_L11_P D6 PLL LOSS Signal 8T49N241_RST B88_L9_P F5 PLL Reset Signal Part 3 8 Gigabit Ethernet Interface There are 2 Gigabit Ethernet ports on the AXU7EV carrier board one is c...

Page 50: ...ransmission of ZYNQ and PHY chip KSZ9031RNX is communicated through the RGMII bus the transmission clock is 125Mhz and the data is sampled on the rising edge and falling samples of the clock When the...

Page 51: ...DIO L34 Ethernet 1 MDIO Management Data PL Gigabit Ethernet pin assignment is as follows Signal Name Pin Name Pin Number Description PHY2_TXCK B65_L14_P AG21 Ethernet 2 RGMII Transmit Clock PHY2_TXD0...

Page 52: ...rface You can use a USB cable to connect it to the PC s USB port for serial data communication The schematic diagram of the USB Uart circuit design is shown in the figure below The schematic diagram o...

Page 53: ...ers of ZYNQ BANK225 and the data rate of each TX transmission and RX reception is up to 12 5Gb s The reference clock of the GTH transceiver is provided by the 125M differential clock of the core board...

Page 54: ...he data level of the SD card is 3 3V connected through the TXS02612 level shifter The schematic of the ZU7EV PS and SD card connector is shown in Figure 3 11 1 Figure 3 11 1 SD Card Connection Diagram...

Page 55: ...Data3 SD_CMD SD_CMD F33 SD card insertion signal Part 3 12 MIPI Camera Interface The AXU7EV carrier board includes a MIPI camera interface which can be used to connect with the ALINX Brand MIPI OV5640...

Page 56: ...CAM_SCL B87_L11_P H7 I2C Clock of Camera CAM_SDA B87_L11_N G7 I2C Data of Camera Part 3 13 FMC Interface The AXU7EV FPGA Carrier board has a standard FMC LPC expansion port that can be connected to va...

Page 57: ...FMC Transceiver Data Receive 0 Negative FMC_DP0_M2C_P 225_RX1_P AB4 FMC Transceiver Data Receive 0 Positive FMC_CLK0_N B28_L11_N E22 FMC Reference 1st Clock Negative FMC_CLK0_P B28_L11_P F22 FMC Refer...

Page 58: ...erence 9th Data N FMC_LA09_P B28_L24_P B20 FMC Reference 9th Data P FMC_LA10_N B28_L22_N B19 FMC Reference 10th Data N FMC_LA10_P B28_L22_P B18 FMC Reference 10th Data P FMC_LA11_N B28_L19_N A19 FMC R...

Page 59: ..._N B64_L21_N AB15 FMC Reference 26th Data N FMC_LA26_P B64_L21_P AB16 FMC Reference 26th Data P FMC_LA27_N B64_L24_N AD16 FMC Reference 27th Data N FMC_LA27_P B64_L24_P AD17 FMC Reference 27th Data P...

Page 60: ...side is show as Figure 3 14 1 Figure 3 14 1 Connection diagram of CAN transceiver chip on PS side The CAN communication pin assignments are as follows Signal Name ZYNQ Pin Name ZYNQ Pin Number Descri...

Page 61: ...Transceiver PL_485_RXD1 B88_L3_P A3 The 1st Channel 485 Receiver PL_485_DE1 B88_L6_N B3 The 1st Channel 485 Transmit Enable PL_485_TXD2 B88_L12_N E5 The 2nd Channel 485 Transceiver PL_485_RXD2 B88_L10...

Page 62: ...week External need to connect a 32 768KHz passive clock to provide an accurate clock source to the internal clock circuit so that the RTC can accurately provide clock information At the same time in o...

Page 63: ...h is connected to the PS terminal through the I2C bus A high precision low power digital temperature sensor chip is installed on the AXU7EV FPGA development board and the model is LM75 from ON Semicon...

Page 64: ...n the AXU7EV Carrier board including 1 power indicator light 1 DONE indicator 1 PS control indicator and 1 PL control indicator The user can control the on and off through the program The schematic di...

Page 65: ...nnected to the IO of the PL The reset KEY and the user KEYs are both low level active The connection diagram of the user key is shown in Figure 3 20 1 Figure 3 20 1 Rest keys connection diagram ZYNQ p...

Page 66: ...figuration is shown in the following table 3 21 1 SW1 Dial Position 1 2 3 4 MODE 3 0 Start mode ON ON ON ON 0000 PS JTAG ON ON OFF ON 0010 QSPI FLASH ON OFF ON OFF 0101 SD Card ON OFF OFF ON 0110 EMMC...

Page 67: ...nd fan to the chip on the board to prevent the chip from overheating The control of the fan is controlled by the ZYNQ chip The control pin is connected to the IO of the BANK88 PIN F4 If the IO level o...

Page 68: ...ZYNQ Ultrascale FPGA Board AXU7EV User Manual 68 68 Amazon Store https www amazon com alinx Part 3 24 Carrier Board Size Dimension Figure 3 24 1 Top View...

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