ZYNQ Ultr FPGA Board AXU7EV User Manual
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PCIe x 4, PCIe x 2, PCIe x 2 data communication.
The transceiver signal of the PCIe interface is directly connected to the
GTH transceiver of FPGA BANK223, BANK224, and the single-channel
communication rate can be as high as 8G bit bandwidth.
The PCIe interface schematic is shown in Figure 3-2-1 below, where the
TX signal is connected in AC coupling mode.
Figure 3-2-1: PCIe Interface Schematic
PCIe x8 Interface FPGA Pin Assignment
Signal Name
FPGA Pin Name
Pin Number
Description
PCIE_RX0_N
223_RX0_N
AP3
PCIE Channel 0 Data Receive Negative
PCIE_RX0_P
223_RX0_P
AP4
PCIE Channel 0 Data Receive Positive
PCIE_RX1_N
223_RX1_N
AN1
PCIE Channel 1 Data Receive Negative
PCIE_RX1_P
223_RX1_P
AN2
PCIE Channel 1 Data Receive Positive