Alinx AC7K325, User Manual, Page: 36 / 45

KINTEX-7 FPGA Development Board AV7K300 User Manual
36 / 45
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GTX transceiver TX of FPGA BANK118 to realize high-speed SDI video output.
The hardware connection diagram of GV8500 chip and FPGA is shown in
Figure 3-4-1:
Figure 3-4-1: SDI Output Interface Schematic
The pin assignment of the 1
st
SDI output:
Signal Name FPGA Pin Pin Number Description
SDI1_3G_TXN BANK118_TX0_N D1 SDI Output Differential Signal Negative
SDI1_3G_TXP BANK118_TX0_P D2 SDI Output Differential Signal Positive
SDI1_SD_HD B18_L3_N L13 SDI Conversion Rate Control
The pin assignment of the 2
nd
SDI output:
Signal Name FPGA Pin Pin
Number
Description
SDI2_3G_TXN BANK118_TX1_N C3 SDI Output Differential Signal Negative
SDI2_3G_TXP BANK118_TX1_P C4 SDI Output Differential Signal Positive
SDI2_SD_HD B18_L3_P L12 SDI Conversion Rate Control