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KINTEX-7 FPGA Development Board AV7K300 User Manual

27 / 45

Amazon Store: https://www.amazon.com/alinx

J31 connector pin assignment

J31 Pin

Signal Name

FPGA Pin

J31 Pin

Signal Name

FPGA Pin

1

B16_L12_N

B25

2

B16_L8_P

C24

3

B16_L12_P

C25

4

B16_L8_N

B24

5

B16_L10_N

A26

6

B16_L16_N

C30

7

B16_L10_P

A25

8

B16_L16_P

D29

9

GND

-

10

GND

-

11

B16_L11_N

C26

12

B16_L7_N

A27

13

B16_L11_P

D26

14

B16_L7_P

B27

15

B16_L13_N

C27

16

B16_L18_N

E30

17

B16_L13_P

D27

18

B16_L18_P

E29

19

GND

-

20

GND

-

21

B16_L21_P

G27

22

B16_L14_N

D28

23

B16_L21_N

F27

24

B16_L14_P

E28

25

B16_L20_N

F28

26

B16_L22_N

F30

27

B16_L20_P

G28

28

B16_L22_P

G29

29

GND

-

30

GND

-

31

B16_L9_P

B28

32

B16_L5_P

F26

33

B16_L9_N

A28

34

B16_L5_N

E26

35

B16_L15_P

C29

36

B16_L24_N

G30

37

B16_L15_N

B29

38

B16_L24_P

H30

39

GND

-

40

GND

-

41

B16_L19_N

H25

42

B16_L23_N

H27

43

B16_L19_P

H24

44

B16_L23_P

H26

45

B16_L1_N

A23

46

B16_L17_P

B30

47

B16_L1_P

B23

48

B16_L17_N

A30

49

GND

-

50

GND

-

51

B16_L2_P

E23

52

B16_L3_N

E25

53

B16_L2_N

D23

54

B16_L3_P

F25

55

B16_L6_N

G24

56

B16_L4_P

E24

57

B16_L6_P

G23

58

B16_L4_N

D24

Summary of Contents for AC7K325

Page 1: ...KINTEX 7 FPGA Development Board AV7K300 User Manual...

Page 2: ...KINTEX 7 FPGA Development Board AV7K300 User Manual 2 45 Amazon Store https www amazon com alinx Version Record Version Date Release By Description Rev 1 0 2021 01 22 Rachel Zhou First Release...

Page 3: ...00Mhz system clock source 16 Part 2 5 2 GTX Reference Clock 17 Part 2 6 LED Light 18 Part 2 7 Power Supply 19 Part 2 8 Size Dimension 22 Part 2 9 Board to Board Pin Definition 22 Part 3 Carrier Board...

Page 4: ...nsion board we have extended a wealth of interfaces for users such as 1 PCIex8 interface 4 SFP interface 2 SDI Output Interface 2 SDI Input Interface 1 UART serial port 1 SD card slot 2 40 pin expansi...

Page 5: ...of XC7K325 4 DDR3 QSPI FLASH Adopt Xilinx s KINTEX 7 series chip model XC7K325TFFG900 Four DDR3 memory chips are connected to the HP port of the FPGA chip Each DDR3 has a capacity of up to 512M bytes...

Page 6: ...and the single channel communication rate can be as high as 5GBaud 4 SFP interfaces The four high speed transceivers of the GTX transceiver of the FPGA are connected to the transmission and reception...

Page 7: ...ion port can be connected to various ALINX modules binocular camera TFT LCD screen high speed AD module etc Expansion ports include 1 5V power supply 2 3 3V power supplies 3 ground and 34 IO ports JTA...

Page 8: ...nd system files The 4 board to board connectors of this core board extend 276 IOs of which the level of 92 IOs of BANK17 and BANK18 can be modified by replacing the LDO chip on the core board to meet...

Page 9: ...d the temperature class is industrial This model is a FGG900 package with 900 pins and a 1 0mm pitch The chip naming rules for Xilinx KINTEX 7 FPGA are shown in Figure 2 2 1 below Figure 2 2 1 The Spe...

Page 10: ...at speeds up to 800MHz data rate 1600Mbps and four DDR3 memory systems are directly connected to the BANK32 BANK33 and BANK34 interfaces of the FPGA The specific configuration of DDR3 SDRAM is shown...

Page 11: ...R3_D0 IO_L13P_T2_MRCC_32 AD18 DDR3_D1 IO_L16N_T2_32 AB18 DDR3_D2 IO_L14P_T2_SRCC_32 AD17 DDR3_D3 IO_L17P_T2_32 AB19 DDR3_D4 IO_L14N_T2_SRCC_32 AD16 DDR3_D5 IO_L17N_T2_32 AC19 DDR3_D6 IO_L13N_T2_MRCC_3...

Page 12: ...32 AC14 DDR3_D27 IO_L20P_T3_32 AA15 DDR3_D28 IO_L23P_T3_32 AA17 DDR3_D29 IO_L22N_T3_32 AD14 DDR3_D30 IO_L23N_T3_32 AA16 DDR3_D31 IO_L20N_T3_32 AB15 DDR3_D32 IO_L22N_T3_34 AK6 DDR3_D33 IO_L23P_T3_34 AJ...

Page 13: ...0 IO_L16P_T2_32 AA18 DDR3_DM1 IO_L12P_T1_MRCC_32 AF17 DDR3_DM2 IO_L6P_T0_32 AE16 DDR3_DM3 IO_L24N_T3_32 Y15 DDR3_DM4 IO_L20P_T3_34 AF7 DDR3_DM5 IO_L7P_T1_34 AF3 DDR3_DM6 IO_L18P_T2_34 AJ3 DDR3_DM7 IO_...

Page 14: ...D8 DDR3_A12 IO_L7P_T1_33 AB10 DDR3_A13 IO_L7N_T1_33 AC10 DDR3_A14 IO_L15P_T2_DQS_33 AJ9 DDR3_BA0 IO_L8N_T1_33 AE8 DDR3_BA1 IO_L9P_T1_DQS_33 AC12 DDR3_BA2 IO_L9N_T1_DQS_33 AC11 DDR3_WE IO_L10P_T1_33 AD...

Page 15: ...ected to the dedicated pins of BANK0 and BANK14 of the FPGA chip The clock pin is connected to CCLK0 of BANK0 and other data and chip select signals are connected to D00 D03 and FCS pins of BANK14 res...

Page 16: ...schematic diagram of the clock circuit design is shown in Figure 2 5 1 Figure 2 5 1 Clock Source in the Core Board Part 2 5 1 200Mhz system clock source The FPGA core board provides a differential 20...

Page 17: ...ic System Clock pin assignments Signal Name FPGA Pin SYS_CLK_P AE10 SYS_CLK_N AF10 Part 2 5 2 GTX Reference Clock The AC7K325 core board provides a 125Mhz reference clock for the GTX transceiver The r...

Page 18: ...BANK117_CLK1_P J8 BANK117_CLK1_N J7 Part 2 6 LED Light There are 2 red LED lights on the AC7K325 core board one of which is the power indicator PWR and the other is the configuration LED DONE The pow...

Page 19: ...5 Amazon Store https www amazon com alinx Figure 2 6 1 LED in core board Schematic Part 2 7 Power Supply The AC7K325 core board power supply voltage is DC5V which is powered by the carrier board The c...

Page 20: ...2 7 1 Power Supply Design Diagram 5V generates 1 0V FPGA core power through the DCDC power chip EM2130L01QI The output current of EM2130 is up to 20A which meets the current demand of the core voltag...

Page 21: ...LDO chip SPX3819 1 8 The VTT and VREF voltages of DDR3 are generated by TPS51200 In addition the IO power supply of BANK17 and BANK18 is generated through 2 SPX3819M5 3 3 Users can change the LDO chi...

Page 22: ...total of 4 high speed expansion ports using 4 120 Pin inter board connectors J29 J32 to connect to the carrier board The connector uses Panasonic s AXK5A2137YG and the corresponding connector model is...

Page 23: ...GND 19 BANK115_TX3_N T1 20 BANK115_RX3_N V5 21 BANK115_TX3_P T2 22 BANK115_RX3_P V6 23 GND 24 GND 25 BANK115_CLK0_N R7 26 BANK115_CLK1_N U7 27 BANK115_CLK0_P R8 28 BANK115_CLK1_N U8 29 GND 30 GND 31 B...

Page 24: ...18_RX1_N D5 81 BANK117_RX1_P H6 82 BANK118_RX1_P D6 83 GND 84 GND 85 BANK117_TX2_N H1 86 BANK118_TX2_N B1 87 BANK117_TX2_P H2 88 BANK118_TX2_P B2 89 GND 90 GND 91 BANK117_RX2_N G3 92 BANK118_RX2_N B5...

Page 25: ...L8_N J12 18 B18_L4_N J13 19 GND 20 GND 21 B18_L9_P J16 22 B18_L12_P G13 23 B18_L9_N H16 24 B18_L12_N F13 25 B18_L16_P F11 26 B18_L10_P H11 27 B18_L16_N E11 28 B18_L10_N H12 29 GND 30 GND 31 B18_L18_P...

Page 26: ...D 81 B17_L24_P C19 82 B17_L23_N A22 83 B17_L24_N B19 84 B17_L23_P B22 85 B17_L18_N F17 86 B17_L12_P F20 87 B17_L18_P G17 88 B17_L12_N E20 89 GND 90 GND 91 B17_L19_N B20 92 B17_L11_N E21 93 B17_L19_P C...

Page 27: ...0 17 B16_L13_P D27 18 B16_L18_P E29 19 GND 20 GND 21 B16_L21_P G27 22 B16_L14_N D28 23 B16_L21_N F27 24 B16_L14_P E28 25 B16_L20_N F28 26 B16_L22_N F30 27 B16_L20_P G28 28 B16_L22_P G29 29 GND 30 GND...

Page 28: ...B15_L2_N L23 82 B15_L21_N N24 83 B15_L2_P L22 84 B15_L21_P P23 85 B15_L13_P K28 86 B15_L12_N K25 87 B15_L13_N K29 88 B15_L12_P L25 89 GND 90 GND 91 B15_L22_N P22 92 B15_L20_N N22 93 B15_L22_P P21 94 B...

Page 29: ...18 B13_L5_P AA27 19 GND U14 20 GND U14 21 B13_L18_P AG30 22 B13_L2_N W28 23 B13_L18_N AH30 24 B13_L2_P W27 25 B13_L21_N AG28 26 B13_L8_P Y30 27 B13_L21_P AG27 28 B13_L8_N AA30 29 GND U14 30 GND U14 3...

Page 30: ...H25 78 B12_L4_P AA22 79 GND U14 80 GND U14 81 B12_L15_N AK25 82 B12_L1_P Y23 83 B12_L15_P AJ24 84 B12_L1_N Y24 85 B12_L17_N AK24 86 B12_L2_P Y21 87 B12_L17_P AK23 88 B12_L2_N AA21 89 GND U14 90 GND U1...

Page 31: ...ace 1 SD card interface 2 way 40 pin expansion port JTAG debug interface 4 independent buttons 4 user LED lights Part 3 2 SFP Interface The AV7K300 FPGA development board has four optical interfaces U...

Page 32: ...N BANK117_RX0_N K5 SFP 1 Data Receiver Negative SFP2_TX_P BANK117_TX1_P J4 SFP 2 Data Transmitter Positive SFP2_TX_N BANK117_TX1_N J3 SFP 2 Data Transmitter Negative SFP2_RX_P BANK117_RX1_P H6 SFP 2 D...

Page 33: ...conforms to the standard PCIe card electrical specifications and can be used directly on the x8 PCIe slot of a normal PC Data communication between PCIEex8 PCIEex4 PCIex2 and PCIex1 can be realized be...

Page 34: ...ve Negative PCIE_RX1_P BANK116_RX2_P P6 PCIE Channel 1 Data Receive Positive PCIE_RX1_N BANK116_RX2_N P5 PCIE Channel 1 Data Receive Negative PCIE_RX2_P BANK116_RX1_P R4 PCIE Channel 2 Data Receive Po...

Page 35: ...PCIE Channel 3 Data Receive Positive PCIE_TX3_N BANK116_TX0_N P1 PCIE Channel 3 Data Receive Negative PCIE_TX4_P BANK115_TX3_P T2 PCIE Channel 4 Data Receive Positive PCIE_TX4_N BANK115_TX3_N T1 PCIE...

Page 36: ...1st SDI output Signal Name FPGA Pin Pin Number Description SDI1_3G_TXN BANK118_TX0_N D1 SDI Output Differential Signal Negative SDI1_3G_TXP BANK118_TX0_P D2 SDI Output Differential Signal Positive SDI...

Page 37: ...o reception at three rates The SDI output signal of the GV8601 chip is directly connected with the GTX transceiver RX of FPGA BANK118 to realize high speed SDI video input The hardware connection diag...

Page 38: ...hip adopts the USB UAR chip of Silicon Labs CP2102GM and the USB interface adopts the MINI USB interface It can be connected to the USB port of the upper PC with a USB cable for independent power supp...

Page 39: ...ed is MicroSD card The schematic diagram of FPGA and SD card connector is shown in Figure 3 7 1 Figure 3 7 1 SD Card Slot Schematic SD Card Slot pin assignment Signal Name FPGA Pin FPGA Pin Number Des...

Page 40: ...ult is 3 3V J18 Expansion Header Pin Assignment J18 Pin Signal Name Pin Number J18 Pin Signal Name Pin Number 1 GND 2 5V 3 IO1_1N M23 4 IO1_1P M22 5 IO1_2N K24 6 IO1_2P K23 7 IO1_3N N24 8 IO1_3P P23 9...

Page 41: ...4 IO2_11P H20 25 IO2_12N F18 26 IO2_12P G18 27 IO2_13N C22 28 IO2_13P D22 29 IO2_14N B20 30 IO2_14P C20 31 IO2_15N F17 32 IO2_15P G17 33 IO2_16N B19 34 IO2_16P C19 35 IO2_17N C21 36 IO2_17P D21 37 GND...

Page 42: ...gnal is high When the button is pressed the button level is low The hardware connection diagram of user LED lights and buttons is shown in Figure 3 9 1 Figure 3 9 1 LEDs and Keys Schematic Pin assignm...

Page 43: ...FPGA programs or firmware to FLASH In order to prevent damage to the FPGA chip caused by hot plugging a protection diode is added to the JTAG signal to ensure that the voltage of the signal is within...

Page 44: ...supplies power to the core board through the inter board connector the current output of the DCDC power supply is 6A and the current output of the other 3 3V is 2A The schematic of the power supply d...

Page 45: ...KINTEX 7 FPGA Development Board AV7K300 User Manual 45 45 Amazon Store https www amazon com alinx Part 3 12 Size Dimension Figure 3 12 1 Carrier Board Size Dimension...

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