KINTEX-7 FPGA Development Board AV7K300 User Manual
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chip TPS82085. The +1.0V used by the GTX transceiver is generated by the
DCDC chip EN6362QI, and the MGT_1.5V power supply is generated by the
LDO chip TPS74401 to generate the +1.2V power supply required by GTX.
+3.3V generates GTX auxiliary power 1.8V through an LDO chip
SPX3819-1-8. The VTT and VREF voltages of DDR3 are generated by
TPS51200. In addition, the IO power supply of BANK17 and BANK18 is
generated through 2 SPX3819M5-3-3. Users can change the LDO chip to
make the IO input and output of these two BANKs to other voltage standards.
Because the power supply of the FPGA has the power-on sequence
requirements, in the circuit design, we have designed according to the power
requirements of the chip. The power-on sequence is +1.0V->+1.8V->(+1.5 V,
+3.3V, VCCIO17, VCCIO18) circuit design to ensure the normal operation of
the chip.