AKM AsahiKASEI AK4675, Manual

Page: 51 / 178

[AK4675]
MS0963-E-00 2008/05
- 51 -
OPERATION OVERVIEW
ﾐ
System Clock (Audio I/F)
There are the following five clock modes to interface with external devices. (
Table 1 and Table 2 .)
Mode
PMPLL bit M/S bit PLL3-0 bits Figure
PLL Master Mode ( Note 78 ) 1 1 See Table 4 Figure 38
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1 0 See Table 4 Figure 39
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
1 0 See Table 4
Figure 40
Figure 41
EXT Slave Mode 0 0 x Figure 42
EXT Master Mode 0 1 x Figure 43
Note 78. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit MCKO pin MCKI pin BICK pin LRCK pin
0 “L”
PLL Master Mode
1
Selected by
PS1-0 bits
Selected by
PLL3-0 bits
Output
(Selected by
BCKO bit)
Output
(1fs)
0 “L”
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
Selected by
PS1-0 bits
Selected by
PLL3-0 bits
Input
(
≥
32fs)
Input
(1fs)
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0 “L” GND
Input
(Selected by
PLL3-0 bits)
Input
(1fs)
EXT Slave Mode 0 “L”
Selected by
FS1-0 bits
Input
(
≥
32fs)
Input
(1fs)
EXT Master Mode 0 “L”
Selected by
FS1-0 bits
Output
(Selected by
BCKO bit)
Output
(1fs)
Table 2. Clock pins state in Clock Mode
ﾐ
Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4675 is power-down mode (PDN pin = “L”) and exits reset state, the AK4675 is in slave mode. After exiting reset
state, the AK4675 goes to master mode by changing M/S bit = “1”.
When the AK4675 is in master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and
BICK pins of the AK4675 should be pulled-down or pulled-up by the resistor (about 100k
Ω
) externally to avoid the
floating state.
M/S bit Mode
0 Slave Mode (default)
1 Master Mode
Table 3. Select Master/Slave Mode