AKM AsahiKASEI AK4675, Manual

Page: 143 / 178

[AK4675]
MS0963-E-00 2008/05
- 143 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H PLL Mode Select 0 FS3 FS2 FS1 FS0 PLL3 PLL2 PLL1 PLL0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 0 1 1 0
PLL3-0: PLL Reference Clock Select (
Table 4 )
Default: “0110”(MCKI pin, 12MHz)
FS3-0: Sampling Frequency Select (See
Table 5 and Table 6 ) and MCKI Frequency Select ( Table 11 )
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H PLL Mode Select 1 BTCLK LP BCKO PS1 PS0 MCKO M/S
PMPLL
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
PMPLL: PLL Power Management
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1:
Master Mode
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
PS1-0: MCKO Output Frequency Select (
Table 9 )
Default: “00”(256fs)
BCKO: BICK Output Frequency Select at Master Mode (
Table 10 )
LP: Low Power Mode
0: Normal Mode (default)
1: Low Power Mode: available at fs=22.05kHz or less.
BTCLK: Clock Mode of Audio CODEC
0: Synchronized to Audio I/F (default)
1: Synchronized to PCM I/F
BTCLK bit is enabled at only PMPLL bit = “0”. When BTCLK bit is “1”, Audio CODEC and the digital block
( Figure 56 ) operate by the clock generated by PLLBT.