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AKM AsahiKASEI AK4675, Manual

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AKM AsahiKASEI AK4675 Manual Download Page 27

 

 

[AK4675] 

MS0963-E-00  

2008/05 

 

- 27 - 

Parameter Symbol

min 

typ 

max 

Units

PLL Slave Mode (PLL Reference Clock = LRCK pin)

 

 

LRCK Input Timing 

 

 Frequency 

fs 

8 

- 

48 

kHz 

 

 

DSP Mode: Pulse Width High 

tLRCKH

tBCK

−

60 - 

1/fs 

−

 tBCK

ns 

 

 

Except DSP Mode: Duty Cycle 

Duty 

45 

- 

55 

% 

 

BICK Input Timing 

 

 Period 

tBCK 

1/(64fs) 

- 

1/(32fs) 

ns 

 

 

Pulse Width Low 

tBCKL 

130 

- 

- 

ns 

 

 

Pulse Width High 

tBCKH

130 

- 

- 

ns 

PLL Slave Mode (PLL Reference Clock = BICK pin)

 

 

LRCK Input Timing 

 

 Frequency 

fs 

8 

- 

48 

kHz 

 

 

DSP Mode: Pulse Width High 

tLRCKH

tBCK

−

60 - 

1/fs 

−

 tBCK

ns 

 

 

Except DSP Mode: Duty Cycle 

Duty 

45 

- 

55 

% 

 

BICK Input Timing 

 

 

Period 

PLL3-0 bits = “0010” 

tBCK 

- 

1/(32fs) 

- 

ns 

 

 

 

PLL3-0 bits = “0011” 

tBCK 

- 

1/(64fs) 

- 

ns 

 

 

Pulse Width Low 

tBCKL 

0.4 x tBCK

- 

- 

ns 

 

 

Pulse Width High 

tBCKH

0.4 x tBCK

- 

- 

ns 

External Slave Mode

 

 

MCKI Input Timing 

 

 Frequency  256fs 

fCLK 

2.048 

- 

12.288 

MHz 

 

  

384fs 

fCLK 

3.072 

- 

18.432 

MHz 

 

  

512fs 

fCLK 

4.096 

- 

13.312 

MHz 

 

  

768fs 

fCLK 

6.144 

- 

19.968 

MHz 

 

  

1024fs 

fCLK 

8.192 

- 

13.312 

MHz 

 

 

Pulse Width Low 

tCLKL 

0.4/fCLK 

- 

- 

ns 

 

 

Pulse Width High 

tCLKH 

0.4/fCLK 

- 

- 

ns 

 

LRCK Input Timing 

 

 Frequency  256fs/384fs 

fs 

8 

- 

48 

kHz 

 

  

512fs/768fs 

fs 

8 

- 

26 

kHz 

 

  

1024fs 

fs 

8 

- 

13 

kHz 

 

 

DSP Mode: Pulse Width High 

tLRCKH

tBCK

−

60 - 

1/fs 

−

 tBCK

ns 

 

 

Except DSP Mode: Duty Cycle 

Duty 

45 

- 

55 

% 

 

BICK Input Timing 

 

 Period 

tBCK 

312.5 

- 

- 

ns 

 

 

Pulse Width Low 

tBCKL 

130 

- 

- 

ns 

 

 

Pulse Width High 

tBCKH

130 

- 

- 

ns 

External Master Mode

 

 

MCKI Input Timing 

 

 Frequency  256fs 

fCLK 

2.048 

- 

12.288 

MHz 

 

  

384fs 

fCLK 

3.072 

- 

18.432 

MHz 

 

  

512fs 

fCLK 

4.096 

- 

13.312 

MHz 

 

  

768fs 

fCLK 

6.144 

- 

19.968 

MHz 

 

  

1024fs 

fCLK 

8.192 

- 

13.312 

MHz 

 

 

Pulse Width Low 

tCLKL 

0.4/fCLK 

- 

- 

ns 

 

 

Pulse Width High 

tCLKH 

0.4/fCLK 

- 

- 

ns 

 

LRCK Output Timing 

 

 Frequency 

fs 

8 

- 

48 

kHz 

 

 

DSP Mode: Pulse Width High 

tLRCKH

- 

tBCK 

- 

ns 

 

 

Except DSP Mode: Duty Cycle 

Duty 

- 

50 

- 

% 

 

BICK Output Timing 

 

 

Period 

BCKO bit = “0” 

tBCK 

- 

1/(32fs) 

- 

ns 

 

 

 

BCKO bit = “1” 

tBCK 

- 

1/(64fs) 

- 

ns 

 

 Duty 

Cycle 

dBCK 

- 

50 

- 

% 

Summary of Contents for AsahiKASEI AK4675

Page 1: ...Audio Interface Format 16bit MSB justified I2 S DSP Mode 2 Playback Function Stereo CODEC Digital Volume 12dB 115 0dB 0 5dB Step Mute Digital ALC Automatic Level Control 36dB 54dB 0 375dB Step Mute S...

Page 2: ...384fs 512fs 768fs or 1024fs MCKI pin 7 Output Master Clock Frequencies 32fs 64fs 128fs 256fs 8 Sampling Rate Stereo CODEC PLL Slave Mode LRCK pin 8kHz 48kHz PLL Slave Mode BICK pin 8kHz 48kHz PLL Slav...

Page 3: ...DTOA SDTIA SAIN1 SAIN3 A D PMSAD Control Register SCL SDA TEST5 PCM I F B SDTOB SDTIB RIN3 IN3 LIN4 IN4 RIN4 IN4 LIN3 IN3 BICKB SYNCB TVDD2 TVDD3 SAIN2 PMSRA PMSRB Stereo Line Out PLLBT PMPCM VCOCBT A...

Page 4: ...SVDDA HPL HPR Charge Pump PVDDA VSS3A PVEE CP CN PMHPL PMCP TVDDA VSS2A SPP SPN ALCA LIN1A RIN1A PMSP SCL VOL VOL TEST3 SPIN PMHPR Int Osc or Ext Clock PMVCMA PDNA PMMHL PMMHR Vol Vol Mixing Selector...

Page 5: ...VCOCBT PVEE SDTOA SYNCA CN PDNA BICKA 8 VSS1 ROUT3 LON VCOMA RIN4 IN4 PVDD VSS2 TVDD2 TVDDA VSS4 MCKIA 7 VBATIN LOUT3 LOP LIN3 IN3 TEST6 DVDD SDA 6 LOUT1 RCP LIN4 IN4 RIN1A MCKO NC SCL 5 RIN3 IN3 RIN...

Page 6: ...dio Serial Data Input Pin K1 GPO1 O General Purpose Output 1 Pin J2 TEST4 O TEST Pin This pin must be open F3 SDTO O Audio Serial Data Output Pin J4 PDN I CODEC Power Down Mode Pin H Power up L Power...

Page 7: ...N O Negative Line Output Pin LODIF bit 1 Full differential Mono Output LOUT3 O Lch Stereo Line Output 3 Pin LODIF bit 0 Single ended Stereo Output B7 LOP O Positive Line Output Pin LODIF bit 1 Full di...

Page 8: ...ge Pump Circuit Negative Voltage Output Pin E10 HPL O Lch Headphone Amp Output Pin B10 HPR O Rch Headphone Amp Output Pin A7 VBATIN I Battery Monitor Input Pin C9 VBATO O Battery Monitor Output Pin C8...

Page 9: ...ROUT2S LOUT2S ROUT1 RCN LOUT1 RCP RIN4 IN4 LIN4 IN4 RIN3 IN3 LIN3 IN3 RIN2 IN2 LIN2 IN2 RIN1 IN1 LIN1 IN1 VCOCBT SAIN1 SAIN2 SAIN3 HPL HPR SPIN SPP SPN LIN1A RIN1A VBATIN VBATO TEST2 These pins msut b...

Page 10: ...Pd1 0 91 W Maximum Power Dissipation Note 13 Ta 70 C Note 15 Pd2 1 18 W Note 2 All voltages with respect to ground Note 3 VSS1 VSS2 VSS3 VSS4 VSS1A VSS2A and VSS3A must be connected to the same analog...

Page 11: ...and PDNA pin must be held to L until all power supply pins are supplied After all power supplies are filled PDN and PDNA pins should be set to H The AK4675 supports the following two cases of partial...

Page 12: ...50 500 750 k Stereo ADC Analog Input Characteristics LIN1 RIN1 LIN2 RIN2 LIN3 RIN3 LIN4 RIN4 pins Stereo ADC IVOL IVOL 0dB ALC OFF Resolution 16 Bits Note 21 0 150 0 176 0 203 Vpp Input Voltage Note 2...

Page 13: ...utput Voltage Note 23 1 78 1 98 2 18 Vpp S N D 0dBFS 72 85 dB S N A weighted 82 92 dB Interchannel Isolation 85 100 dB Interchannel Gain Mismatch 0 1 0 5 dB Load Resistance 25 k Load Capacitance 30 pF...

Page 14: ...UT1 ROUT1 LOUT2S ROUT2S LOUT3 ROUT3 LODIF RCV bits 0 1 0 1 dB Input RCP RCN LOP LON LODIF RCV bits 1 6 dB Full differential Line Input IN1 IN2 IN3 IN4 pins MDIF1 MDIF2 MDIF3 MDIF4 bits 1 Maximum Input...

Page 15: ...tage 0 7Vrms at single ended Input 0 62 0 69 0 76 Vrms PSRR 217Hz Note 31 1kHz Note 31 217Hz Note 32 1kHz Note 32 70 70 100 80 dB dB dB dB Interchannel Isolation 60 80 dB Headphone Analog Volume 1 HPG...

Page 16: ...DA with 100mVpp This is the value of convoluting sinusoidal voltage of 100mVpp Note 36 PSR is applied to SVDDA with 100mVpp This is the value of convoluting sinusoidal voltage of 100mVpp Note 37 The a...

Page 17: ...e Mode and LP bit 0 fs 44 1kHz PMMICL PMMICR PMADL PMADR PMDAL PMDAR PMLO1 PMRO1 PMLO2S PMRO2S PMLO3 PMRO3 PMSAD PMVCM bits 1 PMPLL MCKO PMMP M S PMSRA PMSRB PMPCM bits 0 AVDD 12 1mA typ PVDD 0mA typ...

Page 18: ...FS Note 46 FSO FSI 8kHz 44 1kHz 94 dB Dynamic Range Input 1kHz 60dBFS Note 46 FSO FSI 8kHz 44 1kHz 97 dB Ratio between Input and Output Sample Rate FSO FSI 1 6 1 SRC Characteristics Up Sampling SRC B...

Page 19: ...ameter min typ max Units 10bit SAR ADC Characteristics Resolution 10 Bits No Missing Codes 9 10 Bits Integral Linearity Error 2 LSB DNL 1 LSB Analog Input Voltage Range 0 SAVDD V Offset Error 3 LSB Ga...

Page 20: ...Hz 1 0dB 20 0 kHz 3 0dB 21 1 kHz Stopband SB 25 7 kHz Passband Ripple PR 0 1 dB Stopband Attenuation SA 68 dB Group Delay Note 50 GD 19 1 fs DAC Digital Filter LPF SCF Frequency Response 0 20 0kHz FR...

Page 21: ...B 0 3 1 kHz Stopband SB 4 7 kHz Passband Ripple PR 0 15 dB Stopband Attenuation SA 69 dB Group Delay Note 51 GD 4 ms Down Sampling SRC A fs 16kHz Passband 0 15dB PB 0 3 1 kHz Stopband SB 4 7 kHz Passb...

Page 22: ...4 1kHz Passband 0 1dB PB 0 3 1 kHz Stopband SB 4 7 kHz Passband Ripple PR 0 1 dB Stopband Attenuation SA 69 dB Group Delay Note 51 GD 3 ms Down Sampling SRC A fs 48kHz Passband 0 1dB PB 0 3 1 kHz Stop...

Page 23: ...Stopband Attenuation SA 68 dB Group Delay Note 51 GD 2 ms Up Sampling SRC B fs 16kHz Passband 0 1dB PB 0 3 1 kHz Stopband SB 4 7 kHz Passband Ripple PR 0 1 dB Stopband Attenuation SA 68 dB Group Delay...

Page 24: ...1kHz Passband 0 1dB PB 0 3 1 kHz Stopband SB 4 7 kHz Passband Ripple PR 0 1 dB Stopband Attenuation SA 68 dB Group Delay Note 51 GD 2 ms Up Sampling SRC B fs 48kHz Passband 0 1dB PB 0 3 1 kHz Stopban...

Page 25: ...Output Voltage Except SDA pin Iout 200 A VOL1 0 2 V SDA pin 2 0V DVDD 3 6V Iout 3mA VOL2 0 4 V SDA pin 1 6V DVDD 2 0V Iout 3mA VOL2 20 DVDD V Input Leakage Current Note 58 Iind 2 A Note 59 Iina 2 A N...

Page 26: ...cy fs 8 48 kHz DSP Mode Pulse Width High tLRCKH tBCK ns Except DSP Mode Duty Cycle Duty 50 BICK Output Timing Period BCKO bit 0 tBCK 1 32fs ns BCKO bit 1 tBCK 1 64fs ns Duty Cycle dBCK 50 PLL Slave Mo...

Page 27: ...12 288 MHz 384fs fCLK 3 072 18 432 MHz 512fs fCLK 4 096 13 312 MHz 768fs fCLK 6 144 19 968 MHz 1024fs fCLK 8 192 13 312 MHz Pulse Width Low tCLKL 0 4 fCLK ns Pulse Width High tCLKH 0 4 fCLK ns LRCK In...

Page 28: ...3 tBLR 0 4 x tBCK ns BICK to SDTO BCKP bit 0 tBSD 80 ns BICK to SDTO BCKP bit 1 tBSD 80 ns SDTI Hold Time tSDH 50 ns SDTI Setup Time tSDS 50 ns Audio Interface Timing Right Left justified I2 S Master...

Page 29: ...cept Short Frame tSYD2 80 ns BICKA to SDTOA BCKPA bit 0 tBSD2 80 ns BICKA to SDTOA BCKPA bit 1 tBSD2 80 ns SDTIA Hold Time tSDH2 50 ns SDTIA Setup Time tSDS2 50 ns SYNCA Pulse Width Low tSYL2 0 8 x tB...

Page 30: ...40 ns SYNCA Edge to BICKA Note 66 tSYB2 0 5 x tBCK2 40 0 5 x tBCK2 0 5 x tBCK2 40 ns BICKA to SDTOA BCKPA bit 0 tBSD2 70 70 ns BICKA to SDTOA BCKPA bit 1 tBSD2 70 70 ns SDTIA Hold Time tSDH2 50 ns SD...

Page 31: ...cept Short Frame tSYD3 80 ns BICKB to SDTOB BCKPB bit 0 tBSD3 80 ns BICKB to SDTOB BCKPB bit 1 tBSD3 80 ns SDTIB Hold Time tSDH3 50 ns SDTIB Setup Time tSDS3 50 ns SYNCB Pulse Width Low tSYL3 0 8 x tB...

Page 32: ...40 ns SYNCB Edge to BICKB Note 68 tSYB3 0 5 x tBCK2 40 0 5 x tBCK2 0 5 x tBCK2 40 ns BICKB to SDTOB BCKPB bit 0 tBSD3 70 70 ns BICKB to SDTOB BCKPB bit 1 tBSD3 70 70 ns SDTIB Hold Time tSDH3 50 ns SD...

Page 33: ...400 pF Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 50 ns Power down Reset Timing PDN Pulse Width Note 72 tPD 150 ns PMADL or PMADR to SDTO valid Note 73 tPDV 1059 1 fs PMSRA to SDTOA...

Page 34: ...1 6 3 6V Parameter Symbol min typ max Units MCKIA Input Timing OSCN bit 1 Frequency fCLK 2 048 3 072 MHz Pulse Width Low fCLKL 0 4 fCLK ns Pulse Width High fCLKH 0 4 fCLK ns Power down Reset Timing PD...

Page 35: ...s x 100 dMCK tMCKL x fMCK x 100 BICK tBCK tBCKH tBCKL 50 DVDD dBCK tBCKH tBCK x 100 tBCKL tBCK x 100 Figure 4 Clock Timing PLL EXT Master mode Note 77 MCKO is not available at EXT Master mode LRCK BIC...

Page 36: ...LRCKH tBCK MSB BICK 50 DVDD BCKP 1 BCKP 0 tSDS SDTI VIL1 tSDH VIH1 Figure 6 Audio Interface Timing PLL EXT Master mode DSP mode MSBS 1 LRCK 50 DVDD BICK 50 DVDD SDTO 50 DVDD tBSD tSDS SDTI VIL tSDH VI...

Page 37: ...K VIH1 VIL1 BCKP 0 BCKP 1 Figure 8 Clock Timing PLL Slave mode PLL Reference Clock LRCK or BICK pin DSP mode MSBS 0 1 fs LRCK VIH1 tLRCKH VIL1 tBCK BICK tBCKH tBCKL VIH1 VIL1 tBLR BICK VIH1 VIL1 BCKP...

Page 38: ...KL 50 DVDD dMCK tMCKL x fMCK x 100 Duty tLRCKH x fs x 100 tLRCKL x fs x 100 Figure 10 Clock Timing PLL Slave mode PLL Reference Clock MCKI pin Except DSP mode LRCK BICK SDTO 50 DVDD tBSD tSDS SDTI VIL...

Page 39: ...B MSB VIL1 VIH1 VIL1 VIH1 BICK VIL1 VIH1 BCKP 1 BCKP 0 Figure 12 Audio Interface Timing PLL Slave mode DSP mode MSBS 1 1 fCLK MCKI tCLKH tCLKL VIH1 VIL1 1 fs LRCK VIH1 VIL1 tBCK BICK tBCKH tBCKL VIH1...

Page 40: ...DVDD tLRB tBSD tSDS SDTI VIL1 tSDH VIH1 MSB Figure 14 Audio Interface Timing PLL EXT Slave mode Except DSP mode 1 fs2 VIH2 VIL2 SYNCA tSYH2 tSYL2 dSYC2 tSYL2 x fs2 x 100 tBCK2 tBCKL2 VIH2 tBCKH2 VIL2...

Page 41: ...2 tSYD2 VIH2 BICKA VIL2 BCKPA 0 BCKPA 1 Figure 16 PCM I F A Timing at short and long frame sync SYNCA BICKA SDTOA SDTIA tSYB2 SYNCA VIH2 BICKA VIL2 SDTOA 50 TVDD2 tBSD2 VIH2 VIL2 tBSY2 tSDS2 SDTIA VIH...

Page 42: ...2 VIL2 tBSY2 tSDS2 SDTIA VIH2 VIL2 tSDH2 tSYD2 Figure 18 PCM I F A Timing at MSB justified and I2 S Slave mode 1 fs2 50 TVDD2 SYNCA tSYH2 tSYL2 dSYC2 tSYL2 x fs2 x 100 tBCK2 1 fBCK2 tBCKL2 50 TVDD2 tB...

Page 43: ...L2 tSDH2 50 TVDD2 BICKA BCKPA 0 BCKPA 1 Figure 20 PCM I F A Timing at short and long frame sync Master mode MSBSA 0 tSYB2 SYNCA 50 TVDD2 BICKA SDTOA 50 TVDD2 tBSD2 50 TVDD2 tSDS2 SDTIA VIH2 VIL2 tSDH2...

Page 44: ...VDD2 tSDS2 SDTIA VIH2 VIL2 tSDH2 tSYD2 tMBSY2 Figure 22 PCM I F A Timing at MSB justified and I2 S Master mode 1 fs2 VIH3 VIL3 SYNCB tSYH3 tSYL3 dSYC3 tSYH3 x fs2 x 100 tSYL3 x fs2 x 100 tBCK3 1 fBCK3...

Page 45: ...tSDH3 tSYD3 VIH3 BICKB VIL3 BCKPB 0 BCKPB 1 Figure 24 PCM I F B Timing at short and long frame sync Slave mode MSBSB 0 tSYB3 SYNCB VIH3 BICKB VIL3 SDTOB 50 TVDD3 tBSD3 VIH3 VIL3 tBSY3 tSDS3 SDTIB VIH...

Page 46: ...3 VIL3 tBSY3 tSDS3 SDTIB VIH3 VIL3 tSDH3 tSYD3 Figure 26 PCM I F B Timing at MSB justified and I2 S Slave mode 1 fs2 50 TVDD3 SYNCB tSYH3 tSYL3 dSYC3 tSYL3 x fs2 x 100 tBCK3 1 fBCK3 tBCKL3 50 TVDD3 tB...

Page 47: ...L3 tSDH3 50 TVDD3 BICKB BCKPB 0 BCKPB 1 Figure 28 PCM I F B Timing at short and long frame sync Master mode MSBSB 0 tSYB3 SYNCB 50 TVDD3 BICKB SDTOB 50 TVDD3 tBSD3 50 TVDD3 tSDS3 SDTIB VIH3 VIL3 tSDH3...

Page 48: ...tBSD3 50 TVDD3 tSDS3 SDTIB VIH3 VIL3 tSDH3 tSYD3 tMBSY3 Figure 30 PCM I F B Timing at MSB justified and I2 S Master mode Stop Start Start Stop tHIGH tHD DAT SDA SCL tBUF tLOW tR tF tSU DAT VIH1 VIL1 t...

Page 49: ...PMADR bit tPDV SDTO 50 DVDD Figure 32 Power Down Reset Timing 1 tPD PDN VIL1 Figure 33 Power Down Reset Timing 2 PMSRA bit tPDV2 SDTOA 50 TVDD2 Figure 34 Power Down Reset Timing 3 PMSRB bit tPDV3 SDTO...

Page 50: ...AK4675 MS0963 E 00 2008 05 50 Timing Diagram HP SPK Amp 1 fCLK tCLKL VIH4 tCLKH MCKIA VIL4 Figure 36 MCKIA Input Timing tPD VIL4 PDNA Figure 37 Power down Reset Timing...

Page 51: ...tput 1fs 0 L PLL Slave Mode PLL Reference Clock MCKI pin 1 Selected by PS1 0 bits Selected by PLL3 0 bits Input 32fs Input 1fs PLL Slave Mode PLL Reference Clock LRCK or BICK pin 0 L GND Input Selecte...

Page 52: ...MHz 10k 4 7n 40ms 5 0 1 0 1 MCKI pin 12 288MHz 10k 4 7n 40ms 6 0 1 1 0 MCKI pin 12MHz 10k 10n 40ms default 7 0 1 1 1 MCKI pin 24MHz 10k 10n 40ms 8 1 0 0 0 MCKI pin 19 2MHz 10k 4 7n 40ms 12 1 1 0 0 MCK...

Page 53: ...e after a period of 1 fs When sampling frequency is changed the BICK and LRCK pins do not output irregular frequency clocks but go to L by setting PMPLL bit to 0 MCKO pin PLL State MCKO bit 0 MCKO bit...

Page 54: ...t is enabled by MCKO bit The BICK output frequency is selected between 32fs or 64fs by BCKO bit Table 10 AK4675 DSP or P MCKO BICK LRCK SDTO SDTI BCLK LRCK SDTI SDTO MCKI 1fs 32fs 64fs 256fs 128fs 64f...

Page 55: ...he phase between MCKO and LRCK dose not matter The MCKO pin outputs the frequency selected by PS1 0 bits Table 9 and the output is enabled by MCKO bit Sampling frequency can be selected by FS3 0 bits...

Page 56: ...or P MCKI BICK LRCK SDTO SDTI BCLK LRCK SDTI SDTO MCKO 1fs 32fs Figure 41 PLL Slave Mode 2 PLL Reference Clock LRCK pin MCKI should always be present whenever the ADC or DAC is in operation PMADL bit...

Page 57: ...ault Others Others N A N A N A Not available x Don t care Table 11 MCKI Frequency at EXT Slave Mode PMPLL bit 0 M S bit 0 The S N of the DAC at low sampling frequencies is worse than at high sampling...

Page 58: ...han at high sampling frequencies due to out of band noise The out of band noise can be improved by using higher frequency of the master clock The S N of the DAC output through the LOUT ROUT pins at fs...

Page 59: ...p CODEC SRC blocks of the AK4675 must be reset by bringing the PDN pin L This ensures that all internal registers of CODEC SRC blocks reset to their initial values The ADC enters initialization cycle...

Page 60: ...ing edge of LRCK MSB of SDTI is latched by the falling edge of the BICK just after the output timing of SDTO s MSB Figure 44 default 0 1 MSB of SDTO is output by the falling edge of the first BICK aft...

Page 61: ...2 6 0 14 14 Lch Rch SDTI i 15 2 1 0 15 2 1 0 14 14 Lch Rch LRCK Master Slave Figure 44 Mode 0 Timing BCKP 0 MSBS 0 Rch Lch BICK 32fs SDTO o 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 0 15 5 8 7...

Page 62: ...0 14 14 Lch Rch SDTI i 15 2 1 0 15 2 1 0 14 14 Lch Rch LRCK LRCK Master Slave Figure 46 Mode 0 Timing BCKP 0 MSBS 1 Rch Lch BICK 32fs SDTO o 15 0 1 8 9 11 12 14 15 16 17 24 25 27 26 30 31 0 0 15 5 8 7...

Page 63: ...4 15 14 Don t Care 15 MSB 0 LSB Lch Data Rch Data 15 14 13 7 6 5 4 3 1 0 2 15 14 13 1 0 Figure 48 Mode 1 Timing LRCK BICK 32fs SDTO o SDTI i 0 15 14 15 14 1 10 13 13 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0...

Page 64: ...1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 1 0 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 BICK 64fs 0 1 16 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 SDTO o SDTI i 15 14 Don t Care 2 15 1 15 15 15 Don t Care 15 MSB 0 LS...

Page 65: ...1 1 LIN1 RIN4 0 0 0 0 0 1 0 0 LIN2 RIN1 0 0 0 0 0 1 0 1 LIN2 RIN2 0 0 0 0 0 1 1 0 LIN2 RIN3 0 0 0 0 0 1 1 1 LIN2 RIN4 0 0 0 0 1 0 0 0 LIN3 RIN1 0 0 0 0 1 0 0 1 LIN3 RIN2 0 0 0 0 1 0 1 0 LIN3 RIN3 0 0...

Page 66: ...p Rch PMAINL3 bit PMAINR3 bit PMAINL2 bit PMAINR2 bit PMAINL1 bit PMAINR1 bit LIN4 IN4 pin RIN4 IN4 pin PMLOOPL bit PMLOOPR bit PMAINL4 bit PMAINR4 bit Figure 51 Mic Line Input Selector IN1 pin IN1 pi...

Page 67: ...bits 0 or 30k typ MGNL R0 bits 1 Mode MGNL3 MGNR3 MGNL2 MGNR2 MGNL1 MGNR1 MGNL0 MGNR0 Input Gain Input Resistance 0 0 0 0 0 N A N A 1 0 0 0 1 12dB 30k 2 0 0 1 0 9dB 42k 3 0 0 1 1 6dB 30k 4 0 1 0 0 3d...

Page 68: ...minimum 0 5k In case of using two sets of stereo mic the load resistance is minimum 2k for each channel Any capacitor must not be connected directly to the MPWR pin Figure 54 PMMP bit MPWR pin 0 Hi Z...

Page 69: ...ltage of the MDT pin is higher than 0 075 x AVDD because of the relationship between the bias resistance at the MPWR pin typ 2 2k and the microphone impedance In case of Headphone No Mic the input vol...

Page 70: ...SDTIA SDTOB SDTIB PMSRA PMSRB A D Stereo Separation PMADL or PMADR D A M I X PMDAL or PMDAR or PMSRA ALC 5 band Notch DATT SMUTE PFSEL 0 PMADL or PMADR PFSEL 1 PMDAL or PMDAR or PMSRA LPF HPF SRC A S...

Page 71: ...ack path See 5 band Equalizer 10 DATT Digital Volume for playback path See Digital Output Volume 11 SMUTE Soft mute See Soft Mute 12 DATT B Digital Volume for Recording of Received Voice See Digital V...

Page 72: ...0 bits B MSB F1A13 F1B13 LSB F1A0 F1B0 A 1 tan fc fs 1 1 tan fc fs B 1 1 tan fc fs 1 1 tan fc fs Transfer function H z A 1 z 1 1 Bz 1 The cut off frequency should be set as below fc fs 0 0001 fc min 4...

Page 73: ...d be set when FIL3 bit 0 or PMADL PMADR PMDAL PMDAR bits 0 1 When FIL3 is set to HPF fs Sampling frequency fc Cut off frequency K Filter gain dB 0dB K 10dB Register setting Note 79 FIL3 F3AS bit 0 F3A...

Page 74: ...data passes this block by 0dB gain The coefficient should be set when EQ0 bit 0 or PMADL PMADR PMDAL PMDAR bits 0 fs Sampling frequency fc1 Pole frequency fc2 Zero point frequency K Filter gain dB Max...

Page 75: ...A1 E1B 15 0 bits B1 E1C 15 0 bits C1 EQ2 E2A 15 0 bits A2 E2B 15 0 bits B2 E2C 15 0 bits C2 EQ3 E3A 15 0 bits A3 E3B 15 0 bits B3 E3C 15 0 bits C3 EQ4 E4A 15 0 bits A4 E4B 15 0 bits B4 E4C 15 0 bits C...

Page 76: ...ossing timeout When ZELMN bit 1 zero cross detection is disabled IVL and IVR values are immediately period 1 fs changed by ALC limiter operation Attenuation step is fixed to 1 step regardless of the s...

Page 77: ...375dB x 2 When the IVL and IVR values exceed the reference level REF7 0 bits the IVL and IVR values are not increased When ALC recovery waiting counter reset level LMTH1 0 Output Signal ALC limiter d...

Page 78: ...35 25 E1H 30 0 default 92H 0 375 91H 0 0 90H 0 375 0 375dB 2H 53 625 1H 54 0 0H MUTE Table 29 Reference Level at ALC Recovery Operation RFST1 bit RFST0 bit Recovery Speed 0 0 4 times default 0 1 8 ti...

Page 79: ...step RGAIN1 0 Recovery GAIN step 00 1 step 00 1 step RFST1 0 Fast Recovery Speed 00 4 times 00 4 times ALC ALC enable 1 Enable 1 Enable Table 31 Example of the ALC setting Recording Path fs 8kHz fs 44...

Page 80: ...0 WR IVR7 0 WR REF7 0 WR LMTH1 0 RGAIN1 0 LMAT1 0 ZELMN Example Limiter Zero crossing Enable Recovery Cycle 32ms 8kHz Zero Crossing Timeout Period 32ms 8kHz Limiter and Recovery Step 1 Fast Recovery S...

Page 81: ...annels The IVOL value is changed at zero crossing or timeout Zero crossing timeout period is set by ZTM1 0 bits If IVL7 0 or IVR7 0 bits are written during PMADL PMADR bits 0 IVOL operation starts wit...

Page 82: ...cy but the frequency component lower than 100Hz is controlled Note 82 10kHz is not center frequency but the frequency component higher than 10kHz is controlled EQ bit controls ON OFF of this Equalizer...

Page 83: ...l Rch level This volume has a soft transition function The OVTM bit sets the transition time between set values of OVL R7 0 bits as either 1061 fs or 256 fs Table 37 When OVTM bit 0 a soft transition...

Page 84: ...he OVTM bit after starting the operation the attenuation is discontinued and returned to the value set by the OVL R7 0 bits The soft mute is effective for changing the signal source without stopping t...

Page 85: ...output volume control DATT C 256 levels 0 5dB step Mute for received voice The volume can be set by the CVL7 0 bits The volume is included in front of SDTOB output The input data of SRC C is changed...

Page 86: ...t and output data selection In case of mono operation the same data is output to both channel slots PMADL PMADR ADC Lch data ADC Rch data 0 0 All 0 All 0 default 0 1 Rch Input Signal Rch Input Signal...

Page 87: ...Enable Output default 1 Disable L Table 47 SDTO Disable SDIM1 0 bits select stereo or mono of SDTI input data In case of mono mode the same data is input to both channels SDIM1 SDIM0 Lch Rch 0 0 L R d...

Page 88: ...1 N A Table 52 5 band EQ Rch Input Mixing 2 N A Not available DAM and MIXD bits set the data mixing for DAC input DAM MIXD Lch Rch 0 x L R default 1 0 L R L R 1 1 L R 2 L R 2 Table 53 DAC Mono Mixing...

Page 89: ...B 1 1 N A Table 57 SDTOB Mixing N A Not available When SDOBD bit is 1 SDTOB output data can be disabled fixed to L SDOBD SDTOB 0 Enable Output default 1 Disable L Table 58 SDTOB Disable BVMX1 0 bits s...

Page 90: ...p at MGNL R0 bits 0 and 20k typ at MGNL R0 bits 1 respectively L1G1 0 L2G1 0 L3G1 0 L4G1 0 and LPG1 0 bits adjust the gain for each path Table 60 Table 61 Table 62 Table 63 Table 64 LIN1 IN1 pin ADC L...

Page 91: ...default 0 1 6dB 1 0 6dB 1 1 N A Table 64 MIC Amp Mixing Gain typ N A Not available Analog Mixing Full differential Input IN1 IN1 IN2 IN2 IN3 IN3 IN4 IN4 pins When MDIF1 MDIF2 MDIF3 and MDIF4 bits are...

Page 92: ...1 and LOPS1 bit 0 LOUT1 ROUT1 is in normal operation L1VL2 0 bits control the volume of LOUT1 ROUT1 When LOM bit 1 DAC output signal is output to LOUT1 and ROUT1 pins as L R mono signal When LOOPM bit...

Page 93: ...LO1 PMRO1 bits 1 Stereo line output exits the power down mode LOUT1 and ROUT1 pins rise up to VCOM voltage Rise time is 200ms max 300ms at C 1 F and AVDD 3 3V 3 Set LOPS1 bit 0 after LOUT1 and ROUT1 p...

Page 94: ...LOOPL bit 6 0 6dB 6 0 6dB DATT L1VL2 0 bits LINL4 bit LINL3 bit M I X DACL bit x LOM bit ROUT1 pin RINR2 bit RINR1 bit LOOPL bit x LOOPM bit L1VL2 0 bits RINR4 bit RINR3 bit 0dB DACR bit MIC Amp Rch...

Page 95: ...dB DATT L1VL2 0 bits LINL4 bit LINL3 bit M I X DACL bit x LOM bit ROUT1 pin RINR2 bit RINL1 bit LOOPL bit x LOOPM bit L1VL2 0 bits RINR4 bit RINR3 bit 0dB DACR bit MIC Amp Rch Stereo DAC Rch IN4 pins...

Page 96: ...t power up down can be reduced by changing PMLO1 and PMRO1 bits at LOPS1 bit 0 When PMLO1 PMRO1 bits 1 and LOPS1 bit 0 mono receiver output enters in normal operation L1VL3 0 bits control the volume o...

Page 97: ...pin M I X LINL3 bit LIN4 pin LINL4 bit 0dB DACR bit RCP RCN pins MIC Amp Lch Stereo DAC Rch LIN2 pin LINL2 bit LIN1 pin LINL1 bit LOOPL bit RIN3 pin RINR3 bit RIN4 pin RINR4 bit 0dB DACL bit MIC Amp...

Page 98: ...rcuit MDIF1 MDIF2 MDIF3 MDIF4 bits 1 Stereo Line Output 2 LOUT2S ROUT2S pins Power supply voltage for the LOUT2S ROUT2S is supplied from the AVDD pin and centered on the 0 5 x AVDD typ voltage The loa...

Page 99: ...B LINH1 bit LOOPHL bit 6 0 6dB 6 0 6dB DATT LINH4 bit LINH3 bit M I X DACHL bit x LOM2 bit ROUT2S pin RINH2 bit RINH1 bit LOOPHL bit x LOOPM2 bit RINH4 bit RINH3 bit 0dB DACHR bit MIC Amp Rch Stereo D...

Page 100: ...DATT LINH4 bit LINH3 bit M I X DACHL bit x LOM2 bit RINH2 bit RINH1 bit LOOPHL bit x LOOPM2 bit RINH4 bit RINH3 bit 0dB DACHR bit MIC Amp Rch Stereo DAC Rch IN4 pins IN2 pins 6 0 6dB LOOPHR bit 6 0 6d...

Page 101: ...O3 PMRO3 bits 1 and LOPS3 bit 0 LOUT3 ROUT3 is in normal operation L3VL3 0 bits control the volume of LOUT3 ROUT3 When LOM3 bit 1 DAC output signal is output to LOUT3 and ROUT3 pins as L R mono signal...

Page 102: ...MLO3 PMRO3 bits 1 Stereo line output exits the power down mode LOUT3 and ROUT3 pins rise up to VCOM voltage Rise time is 200ms max 300ms at C 1 F and AVDD 3 3V 3 Set LOPS3 bit 0 after LOUT3 and ROUT3...

Page 103: ...6 0 6dB LINS1 bit LOOPSL bit 6 0 6dB 6 0 6dB DATT L3VL1 0 bits LINS4 bit LINS3 bit M I X DACSL bit x LOM3 bit ROUT3 pin RINS2 bit RINS1 bit LOOPSL bit x LOOPM3 bit L3VL1 0 bits RINS4 bit RINS3 bit 0d...

Page 104: ...ATT L3VL1 0 bits LINS4 bit LINS3 bit M I X DACSL bit x LOM3 bit ROUT3 pin RINS2 bit RINS1 bit LOOPSL bit x LOOPM3 bit L3VL1 0 bits RINS4 bit RINS3 bit 0dB DACSR bit MIC Amp Rch Stereo DAC Rch IN4 pins...

Page 105: ...o VSS1 default 0 1 Normal Operation Normal Operation 0 Power save Fall down to VSS1 1 1 Power save Rise up to VCOM Table 74 Mono Line Output Mode Setting x Don t care Full differential Mono Line Outpu...

Page 106: ...s should be 0 LIN3 pin M I X LINS3 bit LIN4 pin LINS4 bit 0dB DACSR bit LOP LON pins MIC Amp Lch Stereo DAC Rch LIN2 pin LINS2 bit LIN1 pin LINS1 bit LOOPSL bit RIN3 pin RINS3 bit RIN4 pin RINS4 bit 0...

Page 107: ...C Amp Lch Stereo DAC Rch LINS2 bit LINS1 bit LOOPSL bit 0dB DACSL bit MIC Amp Rch Stereo DAC Lch LOOPSR bit 6 0 6dB 6 0 6dB 6 0 6dB 6 0 6dB 6 0 6dB 6 0 6dB DATT DATT L3VL1 0 bits IN3 pins IN1 pins IN4...

Page 108: ...SCN bit 0 when OSCN bit 1 power up time depends on both the MSEL bit setting and the MCKIA frequency Table 75 During power up time the input volume block outputs VCOMA voltage regardless of the input...

Page 109: ...signal level is 0 7Vrms the output voltage is 0 69Vrms 30mW 16 at HPGA4 0 bits 0dB and HPG bit 0dB HPGA3 0 and HPG bits control the output level of headphone amp HPGA4 0 bits can control from 12dB to...

Page 110: ...HPL R HPMTN HPZ Mode HPL R pins x 0 x 0 Power down Mute Pull down by 20 typ default x 0 x 1 Power down Pull down by 25k typ 1 1 0 0 Mute VSS3A 1 1 1 0 Normal Operation Normal Operation Table 78 Headph...

Page 111: ...er Up Time 0 2 048MHz 6m 12288 MCKIA 2 8224MHz 6 5ms 18432 MCKIA 1 3 072MHz 6ms 18432 MCKIA Table 79 Charge Pump Circuit Power Up Time OSCN bit 1 Transition Time PUT1 0 bits set the power up down time...

Page 112: ...at OSCN bit 1 MSEL bit 1 Attenuation step is fixed to 1 step regardless of the setting of LMATA1 0 bits The attenuate operation is executed continuously until the input signal level becomes ALCA limit...

Page 113: ...level exceeds ALCA limiter detection level LMTHA bit the ALCA limiter operation is done immediately When ALCA recovery waiting counter reset level ALCA Output Signal ALCA limiter detection level LMTH...

Page 114: ...4675 MS0963 E 00 2008 05 114 REFA5 0 GAIN dB Step 3FH 19 5 3EH 19 0 3DH 18 5 3CH 18 0 default 19H 0 5 18H 0 0 17H 0 5 02H 11 0 01H 11 5 00H 12 0 0 5dB Table 87 Reference Level at ALCA Recovery Operati...

Page 115: ...1 Typ 32 8ms OSCN bit 0 ALCA ALCA Enable bit 1 Enable Table 88 Example of the ALCA setting The following registers must not be changed during ALCA operation These bits should be changed after ALCA ope...

Page 116: ...p time of the speaker volume block Table 91 after PMSPL or PMSPR bit is set to 1 The speaker volume is powered up as the default value 0dB regardless of the setting of SPKG5 0 bits SPGA5 0 GAIN dB Ste...

Page 117: ...ne Out Figure 85 Example of normal connection for Speaker fc 66Hz 3dB When the input signal level is 0 56Vrms the speaker amp outputs 0 6W The internal default gain is 11 76dB The SPK Amp outputs 0 6W...

Page 118: ...olume after Power up OSCN bit 1 PMSP bits Speaker Amp 0 Power down Hi Z default 1 Power up Output Table 92 Speaker Amp Output State Thermal Shutdown Function When the internal device temperature rises...

Page 119: ...P PMMHL PMMHR PMOSC PMVCMA bits 0 1 The PVEE pin becomes PVEE voltage within 10ms max at OSCN bit 1 or within the time in Table 79 at OSCN bit 1 5 Power up of input volume PMV1 bit 0 1 Input volume se...

Page 120: ...owered down immediately 11 Power down of Charge Pump VCOMA and HP Amp Mixer Selector and the internal clock oscillator in case of OSCN bit 0 PMCP PMMHL PMMHR PMOSC PMVCMA bits 1 0 The PVEE pin goes 0V...

Page 121: ...OSC bits 0 1 OSCN and MSEL bits should be set during this period 3 In case of OSCN bit 0 the external clock MCKIA pin is not needed In case of OSCN bit 1 the external clock MCKIA pin is needed 4 Speak...

Page 122: ...500 s MCKI 2 048MHz or more later in case of OSCN bit 1 MSEL bit 0 1536 MCKIA 500 s MCKIA 3 072MHz or more later in case of OSCN bit MSEL bit 1 10 Signal input to the SPIN pin is prohibited when ALCA...

Page 123: ...ode for both PCM I F A and B When PMPCM bit is 0 the SYNCA BICKA SYNCB and BICKB pins are Hi Z Mode R C at VCOCBT pin PLLBT3 PLLBT2 PLLBT1 PLLBT0 Reference Clock Input Pin Frequency R C Lock Time max...

Page 124: ...erates the required clock for PCM I F from SYNCB or BICKB Generated clocks are output via the SYNCA and BICKA pins AK4675 Phone Module BICKA SDTOA SDTIA SYNCB SDTI SDTO SYNC SYNCA 1fs2 16fs2 or 32fs2...

Page 125: ...shorting out of the slave mode clock pins and master mode clock output After setting the PDN pin H the PCM I F clock pins are the Hi Z state until PMPCM bit becomes 1 The PCM I F clock pins of master...

Page 126: ...Table 107 2 1 0 MSB justified 32fs2 Figure 99 3 1 1 I2 S 32fs2 Figure 100 Table 103 PCM I F A Format Mode FMTB1 FMTB0 Format BICKB Figure 0 0 0 Short Frame Sync 16fs2 See Table 106 default 1 0 1 Long...

Page 127: ...rising edge of the BICKB just after the output timing of SDTOB s MSB Figure 94 Table 106 PCM I F B Format in Mode 0 MSBSA BCKPA Data Interface Format Figure 0 0 MSB of SDTOA is output by the rising ed...

Page 128: ...D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Don t Care Don t Care D15 D14 D15 D14 1 fs2 D15 D14 D15 D14 16bit Linear SDTIA SDTOA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Don t Care Don...

Page 129: ...D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Don t Care D15 D14 D15 D14 1 fs2 D13 D13 D15 D14 D15 D14 16bit Linear SDTIA SDTOA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Don t Care Don t Care D6 D5 D6 D...

Page 130: ...D5 8bit A Law Law D7 D7 SYNCA Slave 1 fs2 SYNCA Master Figure 97 Timing of Long Frame Sync MSBSA bit 1 BCKPA bit 0 Don t Care SDTIA SDTOA BICKA D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D...

Page 131: ...IA i 15 14 13 Don t Care 1 15 15 0 15 14 15 Don t Care 15 MSB 0 LSB 13 1 0 15 Don t Care Don t Care Figure 99 Timing of MSB justified SYNCA BICKA 32fs2 SDTOA o SDTIA i 0 15 14 15 14 1 10 2 3 7 7 6 5 4...

Page 132: ...Phone Call Side Tone Phone Call RX Phone Call RX Recording SDTO Lch SDTI Lch SDTOA SDTIA SDTOB SDTIB A D Stereo Separation D A M I X ALC 5 band Notch DATT SMUTE LPF HPF SRC A SRC B DATT C DATT B SVOLB...

Page 133: ...ing Phone Call Side Tone Phone Call RX Phone Call RX Recording SDTO Lch SDTI Lch SDTOA SDTIA SDTOB SDTIB A D Stereo Separation D A M I X ALC 5 band Notch DATT SMUTE LPF HPF SRC A SRC B DATT C DATT B S...

Page 134: ...that is input the SAIN3 pin In the case of GPOM1 bit 1 the reference voltage input to the SAIN3 pin should be lower than 0 5 x AVDD SAIN1 2 pin GPO1 pin SAIN3 pin L default SAIN3 pin H Table 110 Gene...

Page 135: ...ement Mode SAR ADC Execute Sequence in case that the interrupt function is enabled 1 Select the measurement mode by A1 0 bits and set PMSAD bit 1 to power up SAR ADC 2 Read Addr 5BH so that A D conver...

Page 136: ...TART condition a slave address is sent This address is 7 bits long followed by the eighth bit that is a data direction bit R W Addresses for CODEC and HP SPK Amp are fixed Figure 105 If the slave addr...

Page 137: ...previous data will be overwritten In case of HP SPK Amp blocks if the address exceeds 12H prior to generating stop condition the address counter will roll over to 00H and the previous data will be ov...

Page 138: ...he master does not generate an acknowledge to the data but instead generates stop condition the AK4675 ceases transmission SDA Slave Address S S T A R T R W 1 A C K A C K Data n 1 A C K Data n 2 A C K...

Page 139: ...Conditions SCL FROM MASTER acknowledge DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER 1 9 8 START CONDITION not acknowledge clock pulse for acknowledgement S 2 Figure 112 Acknowledge on the I2 C B...

Page 140: ...Mixing Control SRMXR1 SRMXR0 SRMXL1 SRMXL0 PFMXR1 PFMXR0 PFMXL1 PFMXL0 16H ALC Timer Select 0 RFST1 RFST0 WTM2 WTM1 WTM0 ZTM1 ZTM0 17H ALC Mode Control 0 ZELMN LMAT1 LMAT0 RGAIN1 RGAIN0 LMTH1 LMTH0 1...

Page 141: ...1 E4A15 E4A14 E4A13 E4A12 E4A11 E4A10 E4A9 E4A8 46H E4 Co efficient 2 E4B7 E4B6 E4B5 E4B4 E4B3 E4B2 E4B1 E4B0 47H E4 Co efficient 3 E4B15 E4B14 E4B13 E4B12 E4B11 E4B10 E4B9 E4B8 48H E4 Co efficient 4...

Page 142: ...it is changed from 0 to 1 the initialization cycle 1059 fs 24ms 44 1kHz starts After initializing digital data of the ADC is output PMADR ADC Rch Power Management 0 Power down default 1 Power up PMDAL...

Page 143: ...R W R W R W R W R W Default 0 0 0 0 0 0 0 0 PMPLL PLL Power Management 0 EXT Mode and Power Down default 1 PLL Mode and Power up M S Master Slave Mode Select 0 Slave Mode default 1 Master Mode MCKO Ma...

Page 144: ...fore the channel change SDOD SDTO Disable Table 47 0 Enable default 1 Disable L Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H MIC Signal Select MDIF4 MDIF3 MDIF2 MDIF1 INR1 INR0 INL1 INL0 R W R W R W...

Page 145: ...ain Control Table 19 Default 0101 0dB Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Mixing Power Management 0 0 0 0 0 0 DTMIC PMLOOPR PMLOOPL R W RD RD RD RD RD RD R W R W Default 0 0 0 0 0 0 0 0 PML...

Page 146: ...ower down default 1 Power up PMAINR2 RIN2 Mixing Circuit Power Management 0 Power down default 1 Power up PMAINL3 LIN3 Mixing Circuit Power Management 0 Power down default 1 Power up PMAINR3 RIN3 Mixi...

Page 147: ...lt 1 ON When PMLO1 bit is 1 DACL bit is enabled When PMLO1 bit is 0 the LOUT1 pin goes to VSS1 LINL1 Switch Control from LIN1 to LOUT1 0 OFF default 1 ON LINL2 Switch Control from LIN2 to LOUT1 0 OFF...

Page 148: ...lt 1 ON When PMRO1 bit is 1 DACR bit is enabled When PMRO1 bit is 0 the ROUT1 pin goes to VSS1 RINR1 Switch Control from RIN1 to ROUT1 0 OFF default 1 ON RINR2 Switch Control from RIN2 to ROUT1 0 OFF...

Page 149: ...Control from DAC Lch to LOUT2S 0 OFF default 1 ON LINH1 Switch Control from LIN1 to LOUT2S 0 OFF default 1 ON LINH2 Switch Control from LIN2 to LOUT2S 0 OFF default 1 ON LINH3 Switch Control from LIN...

Page 150: ...Control from DAC Rch to ROUT2S 0 OFF default 1 ON RINH1 Switch Control from RIN1 to ROUT2S 0 OFF default 1 ON RINH2 Switch Control from RIN2 to ROUT2S 0 OFF default 1 ON RINH3 Switch Control from RIN...

Page 151: ...ult 1 ON When PMLO3 bit is 1 DACSL bit is enabled When PMLO3 bit is 0 the LOUT3 pin goes to VSS1 LINS1 Switch Control from LIN1 to LOUT3 0 OFF default 1 ON LINS2 Switch Control from LIN2 to LOUT3 0 OF...

Page 152: ...AC Rch to ROUT3 0 OFF default 1 ON When PMRO3 bit is 1 DACR bit is enabled When PMRO3 bit is 0 the ROUT3 pin goes to VSS1 RINS1 Switch Control from RIN1 to ROUT3 0 OFF default 1 ON RINS2 Switch Contro...

Page 153: ...er down default 1 Power up PMRO1 ROUT1 Power Management 0 Power down default 1 Power up LOPS1 LOUT1 ROUT1 Power Save Mode 0 Normal Operation default 1 Power Save Mode LOM Mono Mixing from DAC to LOUT1...

Page 154: ...R W R W RD RD RD Default 0 0 0 0 0 0 0 0 LOM2 Mono Mixing from DAC to LOUT2S ROUT2S 0 Stereo Mixing default 1 Mono Mixing LOOPM2 Mono Mixing from MIC Amp to LOUT2S ROUT2S 0 Stereo Mixing default 1 Mo...

Page 155: ...ower Management 0 Power down default 1 Power up LOPS3 LOUT3 ROUT3 Power Save Mode 0 Normal Operation default 1 Power Save Mode LOM3 Mono Mixing from DAC to LOUT3 ROUT3 0 Stereo Mixing default 1 Mono M...

Page 156: ...L1 PFMXL0 R W R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 PFMXL1 0 5 band EQ Lch Input Mixing 1 Table 49 Default 00 SDTI PFMXR 1 0 5 band EQ Rch Input Mixing 1 Table 50 Default 00 SDTI SRM...

Page 157: ...IVOLC ALC R W R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 1 0 ALC ALC Enable 0 ALC Disable default 1 ALC Enable IVOLC Input Digital Volume Control Mode Select 0 Independent 1 Dependent defaul...

Page 158: ...is the transition time between OVL R7 0 bits 00H and FFH SMUTE Soft Mute Control 0 Normal Operation default 1 DAC outputs soft muted BIV2 0 SDTIB Input Volume Control Table 41 Default 0H 0dB SRA1 0 SR...

Page 159: ...n Emphasis Filter Coefficient Setting Enable 0 Disable default 1 Enable When FIL3 bit is 1 the settings of F3A13 0 and F3B13 0 bits are enabled When FIL3 bit is 0 FIL3 block is OFF MUTE EQ0 EQ0 Gain C...

Page 160: ...ereo Separation Emphasis Filter Select 0 HPF Default 1 LPF E0A15 0 E0B13 0 E0C15 C0 EQ0 Gain Compensation Filter Coefficient 14bit x 2 16bit x 1 Default 0000H Addr Register Name D7 D6 D5 D4 D3 D2 D1 D...

Page 161: ...tings of E2A15 0 E2B15 0 and E2C15 0 bits are enabled When EQ2 bit is 0 EQ2 block is through 0dB EQ3 Equalizer 3 Coefficient Setting Enable 0 Disable default 1 Enable When EQ3 bit is 1 the settings of...

Page 162: ...B8 42H E3 Co efficient 4 E3C7 E3C6 E3C5 E3C4 E3C3 E3C2 E3C1 E3C0 43H E3 Co efficient 5 E3C15 E3C14 E3C13 E3C12 E3C11 E3C10 E3C9 E3C8 44H E4 Co efficient 0 E4A7 E4A6 E4A5 E4A4 E4A3 E4A2 E4A1 E4A0 45H E...

Page 163: ...R W R W R W R W R W R W R W R W Default 1 0 0 0 1 0 0 0 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 52H EQ Control 10kHz 0 0 0 0 EQE3 EQE2 EQE1 EQE0 R W RD RD RD RD R W R W R W R W Default 0 0 0 0 1 0...

Page 164: ...wer down default 1 Power up PMSRB SRC B Power Management 0 Power down default 1 Power up PMPCM PCM I F Power Management 0 Power down default 1 Power up PLLBT2 0 PLLBT Reference Clock Select PLLBT3 bit...

Page 165: ...Select at Master Mode Table 96 0 16fs2 default 1 32fs2 SDOAD SDTOA Disable Table 56 0 Enable default 1 Disable L Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 55H PCM I F Control 3 SDOBD PLLBT3 MSBSB BC...

Page 166: ...D3 D2 D1 D0 58H Side Tone Volume Control 0 0 0 0 SDOA SVB2 SVB1 SVB0 R W RD RD RD RD R W R W R W R W Default 0 0 0 0 0 0 0 0 SVB2 0 Side Tone Volume Table 40 Default 5H 12dB SDOA SDTOA Output Signal S...

Page 167: ...R W R W R W Default 0 0 0 0 0 0 0 0 PMSAD 10bit ADC Power Management 0 Power down default 1 Power up A1 0 SAR ADC Measurement Mode Table 113 Default 00 SAIN1 GPOE1 General Purpose Output 1 Enable at G...

Page 168: ...Reserved 0 0 0 0 0 0 0 0 0AH Reserved 0 0 0 0 0 0 0 0 0BH Reserved 0 0 0 0 0 0 0 0 0CH Mode Control 1 0 0 MOFF 0 PTS1 PTS0 0 0 0DH Headphone PGA Control 0 HPZ HPMTN HPGA4 HPGA3 HPGA2 HPGA1 HPGA0 0EH S...

Page 169: ...ault 1 Power ON PMOSC I Power Management for Internal Oscillator 0 Power OFF default 1 Power ON PMCP Power Management for Charge Pump Circuit 0 Power OFF default 1 Power ON PMHPL Power Management for...

Page 170: ...ddr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Power Management 2 0 0 0 0 0 0 0 PMV1 R W RD RD RD RD RD RD RD R W Default 0 0 0 0 0 0 0 0 PMV1 Power Management for Input Volume 1 0 Power OFF default 1...

Page 171: ...utdown Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Lch Headphone Mixer 0 0 0 0 0 0 HPLR1 HPLL1 05H Rch Headphone Mixer 0 0 0 0 0 0 HPRR1 HPRL1 R W RD RD RD RD RD RD R W R W Default 0 0 0 0 0 0 0 0...

Page 172: ...Headphone Amp Pull down Control 0 Ground Mode default HPL HPR pins are shorted to VSS3 1 Hi Z Mode HPL HPR pins are pulled down by 25k typ to VSS3 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH Speak...

Page 173: ...ng Counter Reset Level Default 0 Table 82 RGAINA1 0 ALCA Recovery GAIN Step Default 00 1 step Table 86 LMATA1 0 ALCA Limiter ATT Step Default 00 1 step Table 83 ZELMNA Zero Crossing Detection Enable a...

Page 174: ...ST6 DVDD RCP LIN4 MCKO NC RIN3 IN2 MCKI TEST5 IN2 SAIN3 LRCK PDN IN1 IN1 NC TEST3 LIN1A MPWR ROUT2S NC VSS3 SPN SYNCB SDTIB TEST4 SPP TEST2 SDTI TVDDA AK4675EG BICKA MCKIA SDA SCL BICK VSS1A AVDDA SPI...

Page 175: ...sut be connected to the SYNCA BICKA SYNCB and SYNCB pins of the AK4675 These capacitors at the CP CN pins and VSS3A PVEE pins require low ESR Equivalent Series Resistance over all temperature range Wh...

Page 176: ...M VCOMA pins All signals especially clocks should be kept away from the VCOM and VCOMA pins in order to avoid unwanted coupling into the AK4675 3 Analog Inputs The Mic Line and MIN inputs of CODEC blo...

Page 177: ...AGE 5 5 0 1 5 5 0 1 0 5 A B C D E F G 8 7 6 5 4 3 1 83 0 3 0 05 H J 10 9 0 08 S S 0 05 AB S B 0 5 M A 4 5 1 2MAX 0 25 0 05 2 K Material Lead finish Package molding compound Epoxy Interposer material B...

Page 178: ...systemNote2 and AKEMD assumes no responsibility for such use except for the use approved with the express written consent by Representative Director of AKEMD As used here Note1 A critical component is...

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