[AKD4629-A]
<KM101901>
2011/01
AK4118 supplies AK4629’s Master Clock with MCKO1.
No. OCKS1 OCKS0 MCKO1 MCKO2 X’tal
fs
(max)
0 0 0 256fs 256fs 256fs 96
kHz
1 0 1 256fs 128fs 256fs 96
kHz
2 1 0 512fs 256fs 512fs 48
kHz (default)
3 1 1 128fs 64fs 128fs 192
kHz
Table 7 AK4118’s Master Clock Frequency Select (Stereo mode)
Mode CM1
CM0 PLL
X'tal Clock
source
SDTO
0 0 0 ON ON
PLL RX
(default)
1 0 1
OFF ON X'tal DAUX
2 1 0
ON ON PLL RX
ON ON X'tal DAUX
3 1 1 ON ON X'tal DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Table 8
AK4118’s
Clock Operation Mode select
Other jumper pins set up
1. JP81 (GND) : Connection between AGND and DGND.
OPEN : AGND and DGND are separated on the board.
SHORT : AGND and DGND are connected on the board. <Default>
2. JP11 (RX3) : Digital input connector selection for AK4118.
OPT : Optical connector (PORT1) is used, except when Quad Speed Mode for DAC evaluation.
BNC : BNC Jack (J1) is used. <Default>
3. JP12 (TX) : Digital output connector selection for AK4118.
OPT : Optical connector (PORT2) is used.
BNC : BNC Jack (J2) is used. <Default>
4. JP15 (MCLK_SEL): This jumper pin is fixed to SHORT. <Default>
The function of the toggle SW
[SW1] (PDN): Power down of AK4629 and AK4118. Keep “H” during normal operation.
The indication content for
LED
[LE1] Monitor DZF1 pin of the AK4629.
[LE2] Monitor DZF2 pin of the AK4629.
About zero detection of AK4629, please refer to Page 23 of AK4629’s datasheet.
