Akai LCT2662, Service Manual

Page: 88 / 111

PIN DEFINITIONS
Inputs
I
2
C SEL (Pin 1). This pin selects 28h for writing and 29h for
reading when this input is Low(0). When the input is
High(1), the device selects 2Ah for writing and 2Bh for
reading.
SEN (Pin 4).
This pin enables the signal for the SPI mode
of operation on the Serial Control Port. When this pin is Low
(0), the SPI port is disabled and the SDO pin is in the high-
impedance state. Transitions on the SCK and SDA pins are
ignored. SPI mode operation is enabled when SMS is High
(1).
HIN (Pin 5).
For this pin, the Horizontal Sync input signal
at the CMOS level must be supplied. When the device is
used in VIDEO-LOCK mode, the signal pulls the on-chip
VCO within the proper range. The circuit uses the frequency
of this signal, which must be 3% F
h
, but the overall
signal can be of either polarity. When used in the H-lock
mode, the VCO phase locks to the rising edge of this signal.
The HPOL bit of the H Position register can be set to operate
with either polarity of input signal. This signal is usually
the H Flyback signal. The timing difference between HIN
rising edge and the leading edge of composite sync (of VID-
EO input) is one of the factors which affects the horizontal
position of the display. Any shift resulting from the timing
of this signal can be compensated for with the horizontal
timing value in the H Position Register. H-lock is intended
for use when the part is generating an OSD display when
no video signal is present.
SMS (Pin 6).
This pin allows the mode select pin for the Se-
rial Control Port. When this input is at a CMOS High state
(1), the Serial Control Port operates in the SPI mode. When
the input is Low (0), the Serial Control Port operates in the
I
2
C slave mode. In SPI mode, the SEN pin must be tied High.
(See Reset Operation section.)
VIDEO (Pin 7).
This pin is a composite NTSC video input,
1.0V p-p (nom), band limited to 600 kHz. The circuit op-
erates with signal variation between 0.7–1.4V p-p. The po-
larity is sync tips negative. This signal pin should be AC
coupled through a 0.1 µF capacitor, driven by a source im-
pedance of 470 ohms or less.
SCK (Pin 15).
This pin is an input for a serial clock signal
from the master control device. In I
2
C mode operation, the
clock rate is expected to be within I
2
C limits. In SPI mode,
the maximum clock frequency is 10 MHz.
Reset Operation.
When the SMS and SEN pins are both in
the Low (0) state, the part is in the Reset state; therefore, in
the I
2
C mode, the SEN pin can be used as an NReset input.
When SPI mode is used, if three wire operation is required,
both SMS and SEN can be tied together and used as the
NReset input. In either mode, NReset must be held Low (0)
for at least 100 ns.
Input/Output
V
IN
/INTRO (Pin 13).
In external (EXT) vertical lock mode
of operation, the internal vertical sync circuits lock to the
V
IN
input signal applied at this pin. The part locks to the
rising or falling edge of the signal in accordance with the
setting of the V Polarity command. The default is rising
edge. The V
IN
pulse must be at least 2 lines wide.
In INTRO Mode, when configured for internal vertical syn-
chronization, this pin is an output pin providing an interrupt
signal to the master control device in accordance with the
settings in the Interrupt Mask Register.
SDA (Pin 14).
When the Serial Control Port has been set to
I
2
C mode operation, this pin serves as the bidirectional data
line for sending and receiving serial data. In SPI mode op-
eration, the device operates as a serial data input. SPI mode
output data is available on the SDO pin.
Outputs
RED, GREEN, BLUE (Pins 2, 3, 18). These pins are osi-
tive-acting CMOS-level signals.
•
Color Mode: Red, Green, and Blue characters are in-
corporated as video outputs for use in a color receiver
•
Mono Mode: In this mode, all three outputs carry the
character luminance information
Note:
The selection of Color/Mono Mode is user controlled in
bit D
1
of the Configuration Register (Address=00h). (See
Internal Registers section.)
CSync (Pin 8).
Sync slice level. A 0.1 µF capacitor must be
tied between this pin and analog ground V
SS
(A). This ca-
pacitor stores the sync slice level voltage.
LPF (Pin 9). Loop Filter. A series RC low-pass filter must
be tied between this pin and analog ground V
SS
(A). There
must also be second capacitor from the pin to V
SS
(A).