Akai LCT2662, Service Manual, Page: 64 / 111

Pinout Information Pin Descriptions
Table 2-4 provides detailed Display Port pin descriptions.
DGG0 128 I/O SR5
DGPort Green Pixel Data. In dual pixel output mode these pins are the
ODD green outputs. In single pixel output mode these pins are not used.
DGG1 127 I/O SR5
DGG2 126 I/O SR5
DGG3 125 I/O SR5
DGG4 122 I/O SR5
DGG5 121 I/O SR5
DGG6 120 I/O SR5
DGG7 119 I/O SR5
DGB0 118 I/O SR5
DGPort Blue Pixel Data. In dual pixel output mode these pins are the ODD
blue outputs. In single pixel output mode these pins are not used.
DGB1 117 I/O SR5
DGB2 116 I/O SR5
DGB3 115 I/O SR5
DGB4 114 I/O SR5
DGB5 113 I/O SR5
DGB6 112 I/O SR5
DGB7 111 I/O SR5
Table 2-4 Display Port Pin Descriptions
Name Pin(s) Type Function
DCLK 106 OSR
DPort Pixel Clock. Output clock for the display port pixel data. DCLK is
enabled by the DCLKEN bit and can be inverted by the DCPOL bit. DCLK
can be set to run at ½ pixel rate, for dual pixel output mode, by setting the
DCK2EN bit. The DCLK output can be disabled by the DCLKOFF bit
to reduce power consumption.
DCLKNEG 107 OSR • DPort Pixel Clock.
DVS 108 OS
DPort Vertical Sync. DVS can be either active-high or active-low
depending on the VSPOL bit. Width and timing is controlled by the VPLSE
and VDLY registers.
DHS 109 OS
DPort Vertical Sync. DHS can be either active-high or active-low
depending on the HSPOL bit. Sync width can be controlled by the HPLSE
register.
Table 2-3 Display/Graphics Port Pin Descriptions (continued)
Name Pin(s) Type Function