Aiwa XD-DV520, Service Manual

Page: 44 / 51

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IC DESCRIPTION -4/4 (STI5519) -4/6
108 VSS GROUND POWER
109
TRST
5 TEST RESET I
110 TMS TEST MODE SELECT I
111 TDO TEST DATA OUT O
112 TDI TEST DATA IN I
113 TCK TEST CLOCK I
114 PWM2 Pulse Width Modul 2 VSYNC I/O
115 PWM1 Pulse Width Modul 1
BOOT_FROM_ROM
6 I/O
116 PWM0 Pulse Width Modul 0 HSYNC I/O
117 CPU_OE OUTPUT ENABLE I/O
118 CPU_PROCLK SDRAM CLOCK O
119 VDD2_5 2.5V POWER SUPPLY POWER
120 PIX _CLK 27 MHz main clock I
121 VSS GROUND POWER
122 VDD_PLL VDD PLL=2.5V POWER
123 VSS_PLL GND PLL=GND POWER
124 RESET CHIP RESET I
125 IRQ[2] IRQ[2] (MD_IRQ) I
126 IRQ[1] IRQ[1] (ATAPI IRQ) I
127 IRQ[0] IRQ[0] (SERVO_IRQ) I
128 CPU_BE[0] BYTE 0 ENABLE DQM[0] O
129 CPU_BE[1] BYTE 1 ENABLE DQM[1] O
130 CPU_RW READ-NOT WRITE NOT_SDRAM_WE O
131 CPU_WAIT WAIT STATE I
132 CPU_CE[3] CHIP SEL. BANK 3 CS_SUB_BANK3 O
133 CPU_CE[2] CHIP SEL. BANK 2 O
134 CPU_CE[1] CHIP SEL. BANK 1 O
135 CPU_CE[0] DRAM_RAS0 SDRAM_RAS O
136 VDD3_3 3.3 V POWER SUPPLY POWER
137 VSS GROUND POWER
138 CPU_RAS1 DRAM RAS NOT_SDRAM_CS1 I/O
139 CPU_CAS0 DRAM CAS0 SDRAM_CAS
CPU_ADR[22] O
140 CPU_CAS1 DRAM NOT_SDRAM_CS0 O
141 CPU_DATA[0] DATA[0] I/O
142 CPU_DATA[1] DATA[1] I/O
143 CPU_DATA[2] DATA[2] I/O
144 CPU_DATA[3] DATA[3] I/O
145 CPU_DATA[4] DATA[4] I/O
146 CPU_DATA[5] DATA[5] I/O
Pin No. Pin name Main function
Alternate function
Dir func.
Input Output
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