Pin No.
Pin Name
I/O
Description
-39-
IC DESCRIPTION -2/4 (VT3664164T) -1/1
1, 14, 27
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
3, 9, 43, 49
6, 12, 46, 52
15, 39
16
17
18
19
20, 21
22-26, 29-35
28,41,54
36,40
37
38
VDD
DQ0 ~ DQ15
VDDQ
VSSQ
DQM
___
WE
____
CAS
____
RAS
___
CS
BA0, BA1
A0 ~ A11
VSS
NC
CKE
CLK
Power for input buffers and logic circuit inside DRAM.
Multiplexed pins for data output and input.
Separated power from VDD,to improve DQ noise immunity.
Separated power from VSS,to improve DQ noise immunity.
Makes data output Hi-z.Block data input when DQM active.
Enable Enables write operation and row precharge.
____
Latches column addresses on the positive going edge of the CLK with CAS low.
____
Latches row addresses on the positive going edge of the CLK with CAS low.
Disable or enable the command decoder.
Select bank to activate during row address latch time,or bank to read/write during address latch
time.
Multiplexed pins for row and column address.Row address:A0-A11, Column address:A0-A7.
Ground for input buffers and logic circuit inside DRAM.
No Connection
CKE controls the clock activation and deactivation.When CKE is low, Power Down mode,
Suspend mode or Self Refresh mode is entered.
System clock used to sample inputs on the rising edge of clock.
–
I
–
–
I
I
I
I
I/O
I/O
I/O
–
–
I/O
I
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