Aiwa XD-DV520, Service Manual

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IC DESCRIPTION -4/4 (STI5519) -3/6
69 SMI_ADR[0] Adress bus SDRAM O
70 SMI_ADR[10] Adress bus SDRAM O
71 SMI_ADR[11] Adress bus SDRAM O
72 SMI_ADR[12] Adress bus SDRAM O
73 SMI_ADR[13] Adress bus SDRAM O
74 SMI_CS[0] Chip select bank 0 O
75 SMI_CS[1] Chip select bank 1 O
76 SMI_RAS RAS SDRAM O
77 SMI_CAS CAS SDRAM O
78 SMI_WE SDRAM write enable O
79 SMI_DQML DQ MASK EN LOW O
80 SMI_DQMU DQ MASK EN UP O
81 VDD3_3 3.3 V POWER SUPPLY POWER
82 SMI_CLKIN SDRAM CLOCK IN I
83 VSS GROUND POWER
84 SMI_DATA[0] Data bus SDRAM I/O
85 SMI_DATA[1] Data bus SDRAM I/O
86 SMI_DATA[2] Data bus SDRAM I/O
87 SMI_DATA[3] Data bus SDRAM I/O
88 SMI_DATA[4] Data bus SDRAM I/O
89 SMI_DATA[5] Data bus SDRAM I/O
90 SMI_DATA[6] Data bus SDRAM I/O
91 SMI_DATA[7] Data bus SDRAM I/O
92 SMI_DATA[8] Data bus SDRAM I/O
93 SMI_DATA[9] Data bus SDRAM I/O
94 VDD2_5 2.5V POWER SUPPLY POWER
95 SMI_CLKOUT SDRAM CLOCK OUT O
96 VSS GROUND POWER
97 SMI_DATA[10] Data bus SDRAM I/O
98 SMI_DATA[11] Data bus SDRAM I/O
99 SMI_DATA[12] Data bus SDRAM I/O
100 SMI_DATA[13] Data bus SDRAM I/O
101 SMI_DATA[14] Data bus SDRAM I/O
102 SMI_DATA[15] Data bus SDRAM I/O
103 PIO5[3] PIO5[3]
IRB_UHFin
3 I/O
104 PIO5[4] PIO5[4] IRB_PPMout I/O
Right side
105 PIO5[5] PIO5[5]
IRB_drive0orZ
4 I/O
106 Reserved Reserved output O
107 VDD3_3 3.3 V POWER SUPPLY POWER
Pin N¡ Pin name Main function
Alternate function
Dir func.
Input Output
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