Aiwa SX-DV1, Service Manual

Page: 77 / 88

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Pin No. Pin Name I/O Description
56 UWR I/O
µ
P write strobe.
57 URD I/O
µ
P read strobe. (Not used)
58 URST O Reset signal output, active high.
59 UP3_0 I/O Serial receive data/general programmable I/O. (Not used)
60 UP3_1 I/O Serial transmit data/general programmable I/O. (Not used)
61 UP3_2 I/O External interrupt 0/general programmable I/O. (Not used)
62 UINT O
µ
P interrupt. (Not used)
63 UP3_4 I/O Timer 0 input/general programmable I/O. (Not used)
64 UP3_5 I/O Timer 1 input/general programmable I/O. (Not used)
65 DVDD3 – +3.3V digital supply.
66 XTALI I Crystal input. The working frequency is 33.8MHz.
67 XTALO O Crystal output.
68 DVSS – Digital ground.
69 DQM I/O SDRAM I/O mask. (Not used)
70 BA1 I/O SDRAM bank address 1. (Not used)
71 BA0 O SDRAM bank address 0. (Not used)
72 CKE O SDRAM clock enable. (Not used)
73 CLK O SDRAM clock. (Not used)
74 ~ 75 RA11 ~ RA10 O RAM address bus. (Not used)
76 DVDD – +5V digital supply.
77 ~ 83 RA6 ~ RA0 O RAM address bus.
84 DVDD3 – +3.3V digital supply.
85 ~ 86 RA7 ~ RA8 O RAM address bus.
87 DVSS – Digital ground.
88 RA9 O RAM address bus.
89 RAS O RAM row address strobe.
90 ROE O RAM output enable.
91 RWE O RAM write enable (low).
92 CASH/RWEH O RAM column address strobe / Write enable high.
93 CAS O RAM column address strobe (low).
94 DVDD3 – +3.3V digital supply.
95 ~ 96 RD7 ~ RD8 I/O RAM data bus.
97 RD6 I/O RAM data bus.
98 RD9 I/O RAM data bus.
99 RD5 I/O RAM data bus.
100 RD10 I/O RAM data bus.
101 DVSS – Digital ground.
102 RD4 I/O RAM data bus.
103 RD11 I/O RAM data bus.
104 IPLLVDD - Power pin for system varipitch circuitry.
105 IPLLVSS - Ground pin for system varipitch circuitry
IC DESCRIPTION -3/5 (IC, MT1388E -2/5) XD-DV1
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