Aiwa SX-DV1, Service Manual

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Pin No. Pin Name I/O Description
74 SMI_CSO O Chip select for SDRAM.
75 NC – Not used
76 SMI_RAS O SDRAM row address strobe.
77 SMI_CAS O SDRAM column address strobe.
78 SMI_WE O SDRAM write enable.
79 SMI_DQML O SDRAM DQ mask enable low.
80 SMI_DQMU O SDRAM DQ mask enable up.
81 VDD3_3 – +3.3V power supply.
82 SMI_CLKIN I SDRAM master clock in.
83 VSS – Ground.
84 ~ 93 DQ0 ~ DQ9 I/O SDRAM data bus.
94 VDD2_5 – +2.5V power supply.
95 SMI_CLK O SDRAM master clock out.
96 VSS – Ground.
97 ~ 102 DQ10 ~ DQ15 I/O SDRAM data bus.
103 ~ 105 PIO5-3 ~ PIO5-5 I/O Not used.
106 RESERVE O Reserve output. (Not used)
107 VDD3_3 – +3.3V power supply.
108 VSS – Ground.
109 TRST I Test reset.
110 TMS I Test mode select.
111 TDO O Test data out.
112 TDI I Test data in.
113 TCK I Test clock in.
114 NC – Not connected.
115 XLINK/ROM I/O Connected to pull-up resistor.
116 NC – Not connected.
117 F_OE I/O FLASH ROM output enable.
118 SD_CLK O Not used.
119 VDD2_5 – +2.5V power supply.
120 CLK_27MHZ I 27MHz main clock.
121 VSS – Ground.
122 VDD_PLL – +2.5V power supply for PLL.
123 VSS_PLL – Ground for PLL.
124 3V3_RESET I Chip reset.
125 IRQ2 I Connected to pull-up resistor.
126 IRQ1 I Host interrupt.
127 FPIRQ I SCI request.
128 F_WE/DQM0 O FLASH ROM write enable.
129 DQM1 O Not used.
130 RDNOTWR O Read-not write.
IC DESCRIPTION -4/5 (IC, STi5580 -3/4) XD-DV1
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