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interface instance that currently has the lock, and may be queried from any interface by sending
an “IFLOCK?” command. The reply to this query will be “-1” if the lock is owned by another
interface instance, “0” if the interface is free and “1” if the lock is owned by the requesting
interface instance. Sending any command from an interface without control privileges that
attempts to change the instrument status will set bit 4 of the Standard Event Status Register
and put 200 into the Execution Error Register to indicate that there are not sufficient privileges
for the required action.
Note:
it is also possible to configure the privileges for a particular interface to either ‘read only’
or ‘no access’ from the Web page interface.
12.2.7
Status Reporting
The standard status and error reporting model described in IEEE Std. 488.2 was designed for
the GPIB interface and contains some features intended for use with the Service Request and
Parallel Poll hardware capabilities of that interface, and to accommodate its semi-duplex
operation. Although those facilities are of little use with other interfaces, this instrument makes
the full set of capabilities available to all of the interfaces. A separate set of many of the status
and error registers is maintained for each potential interface instance. The GPIB, USB and
RS232 interfaces each provide a single instance, while the LAN interface provides three: one
for the Web page and one each for the two TCP socket interfaces. Having a separate status
model for each interface instance ensures that data does not get lost, as some status query
commands (e.g. ‘*ESR?’) clear the contents of a register after reading the present value.
The full set of error and status registers and the individual bits they contain is shown in the
Status Model Diagram and described in detail below, but in brief the status is maintained using
five primary registers, the Limit Event Status Register for each output, the Standard Event
Status Register and the Execution Error Register. A summary is reported in the Status Byte
Register, as selected by four masking registers, the Limit Status Enable Register for each
output and the Standard Event Status Enable Register. Two further mask registers, the Service
Request Enable register and the Parallel Poll Response Enable register, control operation of
the GPIB hardware Service Request and Parallel Poll (and the associated
ist
message)
respectively. It is recommended that, when controlling the unit through any interface other than
GPIB, the controller program should simply read the primary status registers directly.
The Standard Event Status Register, supported by the Execution Error and Query Error
registers, records events concerned with command parsing and execution, and the flow of
commands, queries and responses across the interface. These are mainly of use during
software development, as a production test procedure should never generate any of these
errors.
Limit Event Status and Limit Event Status Enable Registers
This pair of registers are implemented for each output as an addition to the IEEE Std.488.2.
Their purpose is to inform the controller of entry to and/or exit from current or voltage limit
conditions and the history of protection trip conditions since the last read.
Any bits set in the Limit Event Status Register (LSR<
N
>) which correspond to bits set in the
Limit Event Status Enable Register (LSE<
N
>) will cause the LIM<
N
> bit to be set in the Status
Byte Register, where <
N
> is 1 for output 1, 2 for output 2 and 3 for output 3.
The Limit Event Status Register is read and cleared by the LSR<
N
>? command. The Limit
Event Status Enable Register is set by the LSE<
N
> <
NRF
> command and read by the LSE<
N
>?
command.
