25
Status Reporting
A separate error and status model is maintained for each interface instance; an interface instance
is defined as a potential connection. USB, RS232 and GPIB are inherently single connections so
represent one interface instance each. LAN, however, allows for multiple simultaneous
connections and therefore represents multiple interface instances. Two interface instances are
allocated to the two TCP socket interfaces and one more is allocated to the Web page interface.
Having a separate model for each interface instance ensures that data does not get lost as many
commands e.g. ‘*ESR?’ clear the contents on read.
Error status is maintained using a set of registers; these are described in the following paragraphs
and shown on the Status Model at the end of this section.
Standard Event Status and Standard Event Status Enable Registers
These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Standard Event Status Register which correspond to bits set in the Standard
Event Status Enable Register will cause the ESB bit to be set in the Status Byte Register.
The Standard Event Status Register is read and cleared by the *ESR? command. The Standard
Event Status Enable register is set by the *ESE <
NRF
> command and read by the *ESE?
command.
It is a bit field where each bit has the following significance.
Bit 7:
Power On. Set when power is first applied to the instrument.
Bit 6:
User Request (Not used).
Bit 5:
Command Error. Set when a syntax type error is detected in a command from the bus.
The parser is reset and parsing continues at the next byte in the input stream
Bit 4:
Execution Error. Set when an error is encountered while attempting to execute a
completely parsed command. The appropriate error number will be reported in the
Execution Error Register, see Error Messages section
Bit 3:
Verify Timeout Error. Set when a parameter is set with 'verify' specified and the value is
not reached within 5 seconds, e.g. output voltage is slowed by a large capacitor on the
output.
Bit 2:
Query Error. Set when a query occurs. The appropriate error number will be reported in
the Query Error Register, see Query Error Register section.
Bit 1:
Not used.
Bit 0:
Operation Complete: Set in response to the ‘*OPC’ command.
Execution Error Register
This register contains a number representing the last error encountered over the current interface.
The Execution Error Register is read and cleared using the ‘EER?’ command. On power up this
register is set to 0 for all interface instances.
Error messages have the following meaning:
0:
No error encountered
1-9:
Internal hardware error detected.
100:
Range error. The numeric value sent is not allowed. This includes numbers that are too
big or too small for the parameter being set and non-integers being sent where only
integers are allowed.
101:
A recall of set up data has been requested but the store specified contains corrupted
data. This indicates either a hardware fault or a temporary data corruption, which can be
corrected by writing data to the store again.
102:
A recall of set up data has been requested but the store specified does not contain any
data.
Summary of Contents for CPX400S
Page 1: ...CPX400S SA SP PowerFlex DC Power Supply ...
Page 28: ...27 Status Model ...
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