V28B Chapter 3 BIOS Setup
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3-5 DRAM Settings
The first chipset settings deal with CPU access to dynamic random access memory (DRAM).
The default timing have been carefully chose and should only be altered if data is being lost. Such
a scenario might well occur if your system had mixed speed DRAM chips installed so that greater
delays may be required to preserve the integrity of the data held in the slower memory chips.
3-5.1 DRAM Clock
The default value for this item is Host Clk.
Host Clk
DRAM Clock equals to host (system clock).
HCLK-33M
DRAM Clock equals to host clock minus 33Mhz.
3-5.2 SDRAM Cycle Length
The item allows you to select the value for SDRAM Cycle delay time. The
default value is 3ns.
The selections are: 2ns and 3ns.
3-5.3 Bank Interleave
The choice: Disabled, Enabled.
3-5.4 Memory Hole 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it can not be cached. The user information of peripherals that need to use this areas of
system memory usually discussed their memory requirement.
The choice: Enabled, Disabled.
3-5.5 P2C/C2P Concurrency
Select Enabled allows caching of the system BIOS ROM at F000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system error
may result.
Enabled
BIOS access cached
Disabled
BIOS access not cached
Summary of Contents for V28B
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