AGP V28B, Manual

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V28B Chapter 3 BIOS Setup
33
3-4.3 Advanced Chipset Features
CMOS Setup Utility – Copyright © 1984 – 2001 Award Software
Advanced Chipset Features
DRAM clock [Host Clk]
DRAM Timing by SPD [Enabled]
SDRAM Cycle Length [3]
BANK Interleave
[Disabled]
Memory Hole [Enabled]
P2C/ C2P Concurrency [Enable]
Fast R-W Turn Around [Disabled]
System BIOS Cacheable [Disabled]
Video RAM Cacheable [Disabled]
Frame Buffer Size [8M]
AGP Buffer Size [8M]
On chip USB
[Enabled]
USB Keyboard Support [Enabled]
Onchip Sound [Enabled]
Onchip Modem [Enabled]
CPU to PCI write Buffer [Enabled]
PCI Dynamic Battery [Disabled]
PCI Master 0 W S write [Enabled]
PCI Delay Transaction [Disabled]
PCI # 2 Access # 1 Retry [Enabled]
AGP Master 1 WS Write [Disabled]
AGP Master 1 WS Read [Disabled]
Memory Parity /ECC Check [Disabled]
Item Help
_____________________
Menu Level
↑↓←→
Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-safe defaults F7:Optimized Defaults
This selection allows you to configure the system based on the specific features of the
installed chipset. This chipset manages bus speeds add access to system memory resources, such
as DRAM and the external cache. If also coordinates communications between the conventional
ISA bus and the PCI bus. It must be stated that these items should never need to be altered. The
default settings have been chosen because they provide the best operating conditions for your
system. The only time you might consider making any change would be if you discovered that
data was being lost while using your system.