V06
3-9.19 PCI#2 Access #1 Retry
When Disabled, PCI#2 will not be disconnected until access finishes (default). When
enabled, PCI#2 will be disconnected if max retries are attempted without success.
The choice: Enabled, Disabled.
3-9.20 AGP Master 1 WS Write
When Enabled, writes to the AGP are executed with one wait states.
The choice: Enabled, Disabled.
3-9.21 AGP Master 1 WS Read
When Enabled, read to the AGP are executed with one wait states.
The choice: Enabled, Disabled.
3-9.22 Memory Parity / ECC Check
This item Enabled to detect the memory parity and error checking & correcting.
The choice: Enabled, Disabled.
3-10 Integrated Peripherals
CMOS Setup Utility – Copyright © 1984 – 2001 Award Software
Integrated Peripherals
On-chip IDE Channel 0
[Enabled]
On-chip IDE Channel 1
[Enabled]
IDE Prefetch Mole
[Disabled]
Primary Master PIO
[Auto]
Primary Slave PIO
[Auto]
Secondary Master PIO
[Auto]
Secondary Slave PIO
[Auto]
Primary Master UDMA
[Auto]
Primary Master UDMA
[Auto ]
Secondary Master UDMA
[Disabled]
Secondary Slave UDMA
[Disabled]
Init Display First
[PCI slot]
IDE HDD Blank Mode
[Disabled]
Onboard FDD Controller
[Enabled]
Onboard Serial Port1
[Auto]
Item Help
Menu Level
If your IDE hard drive
supports block mode select
Enabled for automatic
detection of the optimal
number of block read/write
per sector the drive can
support