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Agilent Technologies E1330B, User'S Manual And Scpi Programming Manual

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54 Understanding the Agilent E1330B Digital I/O Module

Chapter 4

Multiple port handshaking has the following two abnormalities regarding 
the CTL and FLG control lines:

•

Input or Output handshaking using the CTL line.  The CTL line is 

set TRUE or FALSE sequentially on all ports involved in the 
operation, from the lowest numbered port to the highest numbered 
port. A slight time delay exists between each port setting the CTL line 
TRUE or FALSE. When using handshaking on multiple port 
operations, use the highest numbered port CTL line to ensure correct 
data transfer.

•

Input or Output handshaking using the FLG line.  A change in the 

state of any FLG line on any combined port continues the handshake 
operation for all the combined ports. FLG lines can also be electrically 
combined through a jumper setting (see Chapter 2).

Multiple Port

Input/Output

Data input is performed using commands in the SCPI 

MEASure:DIGital:DATA

n subsystem. Data output is performed using the 

commands in SCPI 

[SOURce:]DIGital:DATA

n subsystem.

The returned value of an input, or the TTL levels of an output, will depend 
upon the POLarity programmed.

Both Input and Output operations will attempt to complete the handshake 
mode set and may "hang" if required handshake operations are not 
completed.

The sections “Byte Input” and “Byte Output”, earlier in this chapter, 
describe operations that also apply to multiple port commands. The values 
used for input and output operations depend upon the 

[:type]

 used in the 

command. Values for multiple port output operations are given below.

Table 4-1 shows allowable port combinations for each value of 

[:type]

.

You can combine multiple port operations on the same Digital I/O module. 
For example, you could define two independent 16-bit ports at port 0 and 
port 2.

Input Operations

Output Operations

Format

Range

Format

Range

BYTE

Decimal

0 to 255

Decimal

#H
#Q
#B

-128 to 255
00 to FF
000 to 377
8-bits

WORD

Decimal

-32768

to

32767

Decimal

#H
#Q
#B

-32768 to 32767
0000 to FFFF
00000 to 177777
16-bits

LWORd

Decimal

-2147483648

to

2147483647

Decimal

#H
#Q
#B

-2147483648 to 2147483647
00000000 to FFFFFFFF
0 to 37777777777
32-bits

Summary of Contents for E1330B

Page 1: ...gramming VXIplug play Online Help VXIplug play example programs VXIplug play Online Help VXIplug play function reference VXIplug play Online Help Soft Front Panel information VXIplug play Online Help VISA language information Agilent VISA User s Guide Agilent VEE programming information Agilent VEE User s Manual Supplied with Agilent Command Modules Embedded Controllers and VXLink Agilent E1330B Q...

Page 2: ......

Page 3: ...This Chapter 17 Setting the Address Switch 18 Enabling Pull ups 19 Selecting the Interrupt Line 20 Combining the Flag Lines 21 Digital I O Module Peripheral Pinout 22 Configuring for Isolated Digital I O 25 Connecting to a GPIO Peripheral 26 Using with External Pull ups 28 Typical Connection 29 Chapter 3 Using the Agilent E1330B Digital I O Module 31 Using This Chapter 31 Addressing the Module 31 ...

Page 4: ...ata Bytes and Bits 51 Bit Output 51 Byte Output 52 Multiple Port Operations 53 Multiple Port Handshaking 53 Multiple Port Input Output 54 Chapter 5 Agilent E1330B Digital I O Module Command Reference 57 Using This Chapter 57 Command Types 57 Common Command Format 57 SCPI Command Format 57 Linking Commands 59 SCPI Command Reference 60 DISPlay Subsystem 61 MONitor PORT 61 MONitor PORT 62 MONitor STA...

Page 5: ...ATAn type POLarity 82 DIGital DATAn type POLarity 82 DIGital DATAn type TRACe 83 DIGital DATAn type VALue 84 DIGital DATAn type VALue 85 DIGital FLAGn POLarity 86 DIGital FLAGn POLarity 86 DIGital HANDshaken DELay 87 DIGital HANDshaken DELay 88 DIGital HANDshaken MODE 88 DIGital HANDshaken MODE 89 DIGital IOn 89 DIGital TRACe CATalog 90 DIGital TRACe DATA 90 DIGital TRACe DATA 91 DIGital TRACe DEF...

Page 6: ...rd Status Control Register 111 Port Interrupt Control Register 112 Port Transfer Control Register 113 Port Control Status Register 114 Port Data Register 115 Port Handshake Register 116 Port Delay Register 117 Port Normalization Register 118 A Register Based Output Algorithm 119 A Register Based Input Algorithm 120 Programming Examples 121 System Configuration 121 Resetting the Module 122 Reading ...

Page 7: ...oper site preparation or maintenance 7 TO THE EXTENT ALLOWED BY LOCAL LAW THE ABOVE WARRANTIES ARE EXCLUSIVE AND NO OTHER WARRANTY OR CONDITION WHETHER WRITTEN OR ORAL IS EXPRESSED OR IMPLIED AND AGILENT SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OR CONDITIONS OF MERCHANTABILITY SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE 8 Agilent will be liable for damage to tangible property per ...

Page 8: ...perating personnel must not remove equipment covers or shields Procedures involving the removal of covers or shields are for use by service trained personnel only Under certain conditions dangerous voltages may exist even with the equipment switched off To avoid dangerous electrical shock DO NOT perform procedures involving cover or shield removal unless you are qualified to do so DO NOT operate d...

Page 9: ... A1 1998 EN 61000 4 2 1995 IEC 61000 4 3 1995 EN 61000 4 3 1995 IEC 61000 4 4 1995 EN 61000 4 4 1995 IEC 61000 4 5 1995 EN 61000 4 5 1995 IEC 61000 4 6 1996 EN 61000 4 6 1996 IEC 61000 4 11 1994 EN 61000 4 11 1994 Canada ICES 001 1998 Australia New Zealand AS NZS 2064 1 Limit Group 1 Class A 4kV CD 8kV AD 3 V m 80 1000 MHz 0 5kV signal lines 1kV power lines 0 5 kV line line 1 kV line ground 3V 0 1...

Page 10: ...8 Notes ...

Page 11: ...9 Notes ...

Page 12: ...10 Notes ...

Page 13: ...odule Page 13 Initial Operation Page 16 Technical Description The E1330B Quad 8 Bit Digital I O Module referred to as the Digital I O module is a four port digital input output module intended for data communication and digital control in electronic environments The Digital I O module is compatible with TTL levels 0 5V or CMOS levels using external pull ups The Digital I O module complies with VXI...

Page 14: ... data lines Chapter 2 Configuring the Agilent E1330B Digital I O Module describes how to set these jumpers SCPI commands provided for the Digital I O allow operation on a single bit 8 bit BYTE format 16 bit WORD format using 2 ports or 32 bit LWORd format using 4 ports Table 1 1 shows the mapping of bit numbers from the 8 bit ports to the 16 or 32 bit ports Chapter 5 Agilent E1330B Digital I O Com...

Page 15: ...dable driver The two drivers are slightly different and the differences are detailed in Chapter 5 Agilent E1330B Digital I O Command Reference To use the Agilent E1330B with a C size mainframe and command module you must use a downloadable driver The downloadable driver name for the Digital I O module is DIG_IO The procedure for downloading the drivers is contained in the Agilent E1405B and Agilen...

Page 16: ... be included For example the complete command syntax listing for the first example is DISPlay MONitor STATe 0 1 or OFF ON The item enclosed in brackets STATe does not have to be included for the command to work Complete descriptions of the SCPI command language syntax parameter types and usage are in Chapter 5 of this manual Specifying SCPI Commands SCPI commands related to the Digital I O module ...

Page 17: ...t 0 use the following command MEASure DIGital DATA0 BIT7 For single ports the value of m can range from 0 to 7 Some multiple port operations and commands may allow bit numbers to range from 0 to 31 Specifying Multiple Port Operations The Digital I O module allows you to set or read multiple ports or bits with a single command For example MEASure DIGital DATAn type This command uses an optional key...

Page 18: ... to finish 50 ENTER Dio Ready Hold here until command is finished 60 OUTPUT Dio SOUR DIG FLAG0 POL POS OPC Set POSitive polarity 70 ENTER Dio Ready Wait for finish 80 OUTPUT Dio SOUR DIG FLAG0 POL Query the polarity state 90 ENTER Dio Polarity Get the result 100 IF Polarity POS THEN Check the result 110 DISP Polarity Check ERROR Error discovered 120 PAUSE Pause on error 130 ELSE 140 DISP Polarity ...

Page 19: ...or operation Refer to Figure 2 1 for locations of jumpers and switches This chapter contains the following sections Setting the Address Switch Page 18 Enabling Pull ups Page 19 Selecting the Interrupt Line Page 20 Combining the Flag Lines Page 21 Digital I O Module Peripheral Pinout Page 22 Configuring for Isolated Digital I O Page 25 Connecting to a GPIO Peripheral Page 26 Using with External Pul...

Page 20: ...nd 7 are closed all others are open You can select the address of the Digital I O module to any number 0 255 decimal The default setting of the address switch is shown in Figure 2 2 Note To be recognized as an instrument when you are using the Digital I O module in an Agilent E1300 1301 Mainframe or with an Agilent E1405 or E1406 Command Module the logical address must be set to a multiple of 8 Fi...

Page 21: ...e data lines are outputs and the jumper is in the enabled position the outputs are actively forced high When the data lines are inputs the jumper position makes no difference Note The jumper in the enabled position does not add an input pull up resistor to each data line it enables a chip internal pull up network Each data line has an active resistive terminating network The active circuitry ensur...

Page 22: ...al I O module is factory shipped with the interrupt set to 1 If you need to change the interrupt level you must move both jumpers on the blocks Spare jumpers used for combining the flag FLG lines are stored on the unused ground pins of this connector when it ships from the factory Note The interrupt circuitry for the Agilent E1330B is implemented as release on interrupt acknowledge ROAK The Agilen...

Page 23: ...ine the flag line from multiple ports The combined flag lines are physically tied together An action on any of the combined flag lines performs that action for all combined flag lines Figure 2 5 shows the locations of the flag combining switches and how to set them Before setting any flag combine switches you may wish to read the discussion regarding allowable port combinations and handshaking in ...

Page 24: ...s follows RES Reset Line used to reset a peripheral Output from the Digital I O module STS Status Line used as an auxiliary handshake line Input to the Digital I O module PIR Peripheral Interrupt Line used to signal a peripheral interrupt Input to the Digital I O module FLG Flag Line used to handshake data between a peripheral and the Digital I O module Controlled by the peripheral Input to the Di...

Page 25: ...Configuring the Agilent E1330B Digital I O Module 23 Chapter 2 Figure 2 6 J1 and J2 Connector Pinouts ...

Page 26: ...24 Configuring the Agilent E1330B Digital I O Chapter 2 Figure 2 7 Data Line Location on Ribbon Cables Figure 2 8 Connecting the Digital I O Cable ...

Page 27: ...ows the ribbon cable connections The method of connection to the ribbon cable can be facilitated by the use of specialty fixtures for these connectors but there is no standard for connector keys or spacing For the Opto 22 rack lines 1 10 are not used on the peripheral connector Pins 27 57 on the ribbon cable odd numbered pins only correspond to pins 17 47 on the Opto 22 rack All even numbered pins...

Page 28: ...rectional data transfer The Digital I O module and the GPIO interface have identical line definitions but different pin assignments Ports A D on the GPIO are defined as ports 0 3 on the Digital I O module Procedure 1 Connect the ribbon cable to connector J1 and or J2 on the Digital I O module 2 Connect the wires on the ribbon cable to the peripheral as described in Table 2 1 for the GPIO interface...

Page 29: ...LG1 CTL1 I O1 27 29 31 33 35 37 39 41 3 7 11 15 19 23 4 22 3 21 2 20 1 19 29 8 25 7 30 11 Port 2 Digital I O GPIO Port 3 Digital I O GPIO Connector J2 J1 Connector J2 J1 Name Pin Pin Name Pin Pin D20 D21 D22 D23 D24 D25 D26 D27 RES2 STS2 PIR2 FLG2 CTL2 I O2 43 45 47 49 51 53 55 57 5 9 13 17 21 25 33 15 34 16 35 17 36 18 12 26 9 27 13 31 D30 D31 D32 D33 D34 D35 D36 D37 RES3 STS3 PIR3 FLG3 CTL3 I O3...

Page 30: ... up resistors The internal pull up mode of the Digital I O module should be disabled for open collector output Figure 2 10 shows a single data line connection The value of the pull up resistor is calculated as follows The value of TTL high with the 200 Ωpull up resistor is calculated as follows Figure 2 10 Typical Open Collector Data Line Vcc 5 0 Vdc Imax IoutLow safety_factor 48mA 0 52 25mA R Vcc...

Page 31: ...s have a discrete resistive pull up network The data lines do not have a discrete resistive pull up but can use an internal pull up in the 75ALS160 The internal pull up requires that the data lines sink 3 2 mA to pull the line to less than 0 4 V The I O CTL and RES lines are open collector and require external pull up to logic high Figure 2 11 Typical Driver Receiver Connections ...

Page 32: ...30 Configuring the Agilent E1330B Digital I O Chapter 2 Notes ...

Page 33: ...e 38 Addressing the Module The examples shown in this chapter use the default addresses for the interface Command module and Digital I O module The address uses both GPIB primary and secondary addresses The default address is To establish these defaults as an I O path in BASIC the program examples use this code 10 ASSIGN Dio TO 70918 Each Digital I O module in a system must have a different logica...

Page 34: ...32 Using the Agilent E1330B Digital I O Module Chapter 3 Operation Overview The following steps illustrate general operation of the Digital I O module Figure 3 1 Agilent E1330B General Operation ...

Page 35: ...control line s CTL polarity on port n SOURce DIGital FLAGn POLarity POSitive or NEGative to set the flag line s FLG polarity on port n SOURce DIGital DATAn POLarity POSitive or NEGative to set the data line s polarity on port n Example 10 ASSIGN Dio TO 70918 20 DIM Pol 3 30 Pol POS 40 OUTPUT Dio DIG DATA1 POL Pol 50 END This program sets the polarity to positive on port 1 data lines A TTL high wil...

Page 36: ...shake modes require that a timing value be set Primarily the timing applies to only output functions the exception is STRobe Input handshaking mode These SCPI commands set the timing of the handshake where timing applies SOURce DIGital DATAn type HANDshake DELay time SOURce DIGital HANDshakenDELay time Example 10 ASSIGN Dio TO 70918 20 DIM Hand 4 30 Hand LEAD 40 Delay 0 015 50 OUTPUT Dio DIG DATA0...

Page 37: ...O path to module 20 INTEGER Bits Bytes Ready 30 OUTPUT Dio RST OPC Reset the module to establish defaults 40 ENTER Dio Ready Wait for completion 50 OUTPUT Dio MEAS DIG DATA0 BIT7 Input a bit on port 0 60 ENTER Dio Bits 70 OUTPUT Dio MEAS DIG DATA1 Input a byte on port 1 80 ENTER Dio Bytes 90 DISP Port 0 Bit 7 is Bits Show the results 100 DISP Port 1 byte is Bytes 110 END This example first sets th...

Page 38: ... formats The choice of output format is indicated by a special character in the value to be output If the character is not used the output value is assumed to be in decimal format Example 10 ASSIGN Dio TO 70918 Establish I O path to module 20 INTEGER Bits Bytes Ready 30 Bits 1 40 Bytes 255 50 OUTPUT Dio RST OPC Reset the module to establish defaults 60 ENTER Dio Ready Wait for completion 70 OUTPUT...

Page 39: ...andshake for 32 bit operations 90 ENTER Dio Ready Wait for completion 100 OUTPUT Dio DIG DATA0 LWORD HAND DEL 015 OPC Set handshake delay time 110 ENTER Dio Ready Wait for completion 120 OUTPUT Dio DIG DATA0 LWORD H Pat_1 OPC Set 32 bits use handshake alternating 1 and 0 130 ENTER Dio Ready Wait for completion 140 OUTPUT Dio DIG DATA0 LWORD H Pat_2 OPC Set 32 bits use handshake alternating 0 and 1...

Page 40: ... An Intel processor however when used with the TRACe commands will swap the order the of the bytes The bytes are written or read from memory with the lowest port receiving the most significant byte and the highest port the least significant byte Trace Memory Example 1 This example writes 20 bytes as 10 WORDS at ports 0 and 1 10 RE SAVE Trace_1 20 ASSIGN Dio TO 70918 30 INTEGER A 1 10 Ready 40 DATA...

Page 41: ...TRAC alpha 220 A Fill memory alpha with 20 bytes 140 OUTPUT Dio SOUR DIG DATA0 WORD TRAC alpha OPC Output the 20 bytes 150 ENTER Dio Ready Wait for completion 160 OUTPUT DIO SOUR DIG TRAC DEL alpha OPC Delete memory alpha 170 ENTER Dio Ready Wait for completion 180 END Trace Memory Example 3 This example reads 40 WORDS from ports 0 and 1 10 RE SAVE Trace_3 20 ASSIGN Dio TO 70918 30 DIM Head 4 40 I...

Page 42: ...40 Using the Agilent E1330B Digital I O Module Chapter 3 Notes ...

Page 43: ... I O module ports has 8 data lines and 6 control lines Not all these lines are required for every application A simplified diagram of a port is shown in Figure 1 1 The following subsections describe the use of these lines Data Lines Each port has 8 data lines numbered from 0 to 7 The data lines can be set as an 8 bit group as part of a larger group or individually using SCPI commands The logical T...

Page 44: ...that define handshake modes typically use the FLG and CTL lines The state of the CTL line can be read and set with SCPI commands to implement custom handshakes Positive polarity is the default The following shows the effect of changing the polarity of the CTL line The I O Line Output Each port has an open collector I O line which is output from the Digital I O module to the peripheral and has two ...

Page 45: ...r more information about this line Default and Reset States At initial power on and following the RST command the Digital I O module is set to the following states Setting the Polarity The logical true level of the control CTL line the flag FLG line and the data lines of each port can be set to either TTL high 2 5V or TTL Low 1 4V levels SCPI commands use the POLarity keyword as SOURce DIGital CON...

Page 46: ...handshaking SCPI commands support the following modes of handshaking LEADing Edge TRAiling Edge PULSe PARTial STRobe NONE These SCPI commands set the type of handshake mode used SOURce DIGital DATAn type HANDshake MODE mode SOURce DIGital HANDshaken MODE mode These SCPI commands set the timing of the handshake where timing applies SOURce DIGital DATAn type HANDshake DELay time SOURce DIGital HANDs...

Page 47: ... HIGH 2 The Digital I O module sets the I O line LOW 3 The Digital I O module sets CTL TRUE 3 The Digital I O module places the data on the data lines 4 The peripheral senses the CTL line and places data on the data lines 4 After waiting the programmed delay time Td the Digital I O module sets CTL to TRUE 5 The peripheral sets the FLG line to BUSY indicating data is valid 5 The peripheral senses t...

Page 48: ...the data lines 4 The peripheral senses the CTL line and sets the FLG line to BUSY 4 After waiting the programmed delay time Td the Digital I O module sets CTL to TRUE 5 The Digital I O module senses the FLG BUSY and sets the CTL line FALSE 5 The peripheral senses the CTL line and sets the FLG line to BUSY while it latches the data 6 The peripheral senses the CTL line change and places data on the ...

Page 49: ...E 3 The Digital I O module places the data on the data lines 4 The peripheral senses the CTL line and sets the FLG line to BUSY 4 After waiting the programmed delay time Td the Digital I O module sets CTL to TRUE 5 The peripheral places the data on the data lines and indicates valid data by setting the FLG line to READY 5 The Digital I O module then waits another delay time Td and sets the CTL lin...

Page 50: ...nses the CTL line and sets the data lines 3 After waiting the programmed delay time Td the Digital I O module sets CTL to TRUE 4 The peripheral holds the FLG line READY for at least 250 nsecs and then sets the FLG line BUSY to indicate the data is valid 4 The peripheral senses the CTL line change sets the FLG line to READY for a minimum of 250 nsecs latches the data and sets the FLG line to BUSY 5...

Page 51: ...mmands SOURce DIGital DATAn type HANDshake DELay time or SOURce DIGital HANDshakenDELay time Handshake timing is generally used for data output operations Timing for data input affects only STRobe handshake modes INPUT OUTPUT 1 The Digital I O module sets the I O line HIGH 1 The Digital I O module sets the I O line LOW 2 The Digital I O module sets CTL TRUE 2 The Digital I O module places the data...

Page 52: ...rt POLarity In the default state POSitive polarity a TTL high on the data line specified by m will return a 1 For example the following BASIC program code will request and display the state of data line 3 bit 3 on port 4 120 OUTPUT Dio MEAS DIG DATA4 BIT3 130 ENTER Dio Bits 140 DISP State of bit 3 on port 4 Bits Bit numbers range from 0 to 7 for single port operations For multiple port operations ...

Page 53: ... output operations can accept numbers in decimal hexadecimal octal or binary formats Both Input and Output operations will attempt to complete the handshake mode set for the port and may hang if required handshake operations are not completed To unhang a hung transfer issue a IEEE 488 selected device clear In BASIC this is CLEAR 70918 Bit Output The SCPI command for setting the state of a single b...

Page 54: ...or any bit set to 1 For example the following four BASIC program lines all perform the same function and set the same data lines on port 3 120 OUTPUT Dio DIG DATA3 170 120 OUTPUT Dio DIG DATA3 HAA 120 OUTPUT Dio DIG DATA3 Q252 120 OUTPUT Dio DIG DATA3 B10101010 If port 3 is in the default POSitive polarity mode the TTL levels set on the data lines by any of the program lines above will be Port num...

Page 55: ... will obtain a decimal value of the state of the 32 data lines contained in physical ports 0 1 2 and 3 120 OUTPUT Dio MEAS DIG DATA0 LWORD 130 ENTER Dio Result 140 DISP 32 bit longword at port 4 Result Multiple Port Handshaking The SCPI command syntax to establish a multiple port handshake and set handshake timing is SOURce DIGital DATAn type HANDshake MODE mode SOURce DIGital DATAn type HANDshake...

Page 56: ...sing the commands in SCPI SOURce DIGital DATAn subsystem The returned value of an input or the TTL levels of an output will depend upon the POLarity programmed Both Input and Output operations will attempt to complete the handshake mode set and may hang if required handshake operations are not completed The sections Byte Input and Byte Output earlier in this chapter describe operations that also a...

Page 57: ... 7 0 7 0 Data Lines D0_7 D0_0 D1_7 D1_0 D2_7 D_0 D3_7 D3_0 Parameters value value value value 16 bit WORD operations Port 0 2 Bit Designations 15 8 7 0 15 8 7 0 Data Lines D0_7 D0_0 D1_7 D1_0 D2_7 D_0 D3_7 D3_0 Parameters value value 32 bit LWORd operations Port 0 Bit Designations 31 24 23 16 15 8 7 0 Data Lines D0_7 D0_0 D1_7 D1_0 D2_7 D_0 D3_7 D3_0 Parameters value ...

Page 58: ...56 Understanding the Agilent E1330B Digital I O Module Chapter 4 Notes ...

Page 59: ...n Commands are four or five characters in length always begin with the asterisk character and may include one or more parameters The command keyword is separated from the first parameter by a space character Some examples of Common Commands are shown below RST ESR 32 STB SCPI Command Format SCPI commands perform functions like closing switches making measurements querying instrument states or retr...

Page 60: ...r lower case letters Therefore MEASURE measure and MeAsUrE are all acceptable Command keywords can be entered in their full form as shown above or can be entered in their short form In this manual the entry required in short form commands is always capitalized The short form is generally used for examples in this manual Implied Commands Implied commands are those which appear in square brackets in...

Page 61: ...pe with an all lower case keyword For example in the SCPI command MEASure DIGital DATAn type the keyword type should be replaced by one these parameters BYTE WORD LWORd Linking Commands Linking IEEE 488 2 Common Commands with SCPI Commands Use a semicolon between the commands For example RST DIG CONT2 1 or DIG CONT2 POL POS OPC Linking Multiple SCPI Commands Use both a semicolon and a colon betwee...

Page 62: ...Command Reference Chapter 5 SCPI Command Reference This section describes the Standard Commands for Programmable Instruments SCPI commands for the Digital I O Module Commands are listed alphabetically by subsystem and within each subsystem ...

Page 63: ... line state of the flag line values on the data lines in both decimal and hexadecimal Syntax DISPlay MONitor PORT port AUTO MIN MAX DEF PORT MAX MIN DEF STATe mode STATe MONitor PORT DISPlay MONitor PORT port AUTO MIN MAX DEF sets the displayed port number Parameters Comments In the AUTO mode of operation the display shows the state of the port last programmed MIN sets port 0 MAX sets port 3 No pa...

Page 64: ...itor STATe mode turns the monitor mode ON or OFF Parameters Comments DISPlay MONitor ON or DISPlay MONitor 1 enables the terminal display of port parameters The parameters are updated to the terminal following each new command accessing a port DISPlay MONitor OFF or DISPlay MONitor 0 turns the monitor mode OFF A keyboard entry at the terminal will set DISP MON OFF This command does not perform an ...

Page 65: ...gilent E1330B Digital I O Module Command Reference 63 Chapter 5 MONitor STATe DISPlay MONitor STATe returns a number indicating whether the monitor mode is enabled or disabled 1 ON 0 OFF Parameters None ...

Page 66: ...completion of the handshake MEASure DIGital DATAn LWORd BITm reads the state on bit m of the 32 bit port n after the completion of the handshake Parameters Comments Input data is always assumed to be in binary format since only a single bit of data is being read The command returns either a 0 or 1 The keyword LW32 may be used instead of LWORd when using the downloaded version of the SCPI driver DA...

Page 67: ...k must have been previously defined by the SOURce DIGital TRACe DEFine command This command will completely fill the named block The defined block size sets the amount of data read The block size must by an integer multiple of the type keyword used in this command For example valid block sizes for LWORd are 4 8 12 16 etc Input data is returned in decimal format Other formats are not supported for ...

Page 68: ...the Digital I O may be in binary octal decimal or hexadecimal The keyword LW32 may be used instead of LWORd when using the downloaded version of the SCPI driver Chapter 4 Understanding the Agilent E1330B Digital I O Module describes the byte order of multiple byte reads DATAn is the keyword used for commands relating to the data at port n The port number n must be the last character of the keyword...

Page 69: ...n is the keyword used for commands relating to the flag line at port n The port number n must be the last character of the keyword without spaces If n is omitted FLAG0 is used MEASure DIGital FLAGn may be affected by the condition of the flag combining jumpers Refer to Chapter 2 for additional information Related Commands SOURce DIGital CONTroln POLarity SOURce DIGital CONTroln VALue SOURce DIGita...

Page 70: ... STATe DELete MACRo MEMory DELete MACRo name deletes a single macro previously recorded using the DMC common command Parameters Comments name must have been previously defined by a DMC Define Macro common command The maximum length for name is 12 characters This command purges a single specific macro the PMC common command purges all macros Example MEM DEL MACR test_macro deletes macro named test_...

Page 71: ... VME STATe command Related Commands SOURce DIGital TRACe DEFine MEMory VME ADDress MEMory VME SIZE MEMory VME STATe RST Condition H200000 Example MEM VME ADDR H200000 sets the starting VME address to 20000016 VME ADDRess MEMory VME ADDRess MIN MAX queries for the current VME memory address The optional parameter lets you query for the fixed minimum or maximum address Parameters Comments This comma...

Page 72: ...T Condition H000000 VME SIZE MEMory VME SIZE MIN MAX queries for the current VME memory size The optional parameter lets you query for the fixed maximum or minimum VME memory size Parameters Comments This command always returns the memory size in decimal format The size returned using MIN is always 0 The size returned using MAX is always 12582912 Related Commands MEMory VME ADDRess MEMory VME SIZE...

Page 73: ...TRACe DATA MEMory VME ADDress MEMory VME SIZE RST Condition Set to OFF Example MEM VME STAT ON enables access to the VME memory VME STATe MEMory VME STATe queries the state of the external memory Parameters None Comments This command returns 0 or 1 indicating external memory is OFF or ON Related Commands MEMory VME ADDRess MEMory VME SIZE Parameter Name Parameter Type Range of Values Default Value...

Page 74: ...e and handshake delay for both data input and output The root command SOURce is optional SOURce DIGital CONTroln POLarity POS NEG POLarity VALue 0 1 or ON OFF VALue DATAn BYTE BITm 0 1 BITm HANDshake DELay time DELay MODE NONE LEADing TRAiling PULSe PARTial STRobe MODE POLarity POS NEG POLarity TRACe name VALue base value VALue LWORd BITm 0 1 BITm HANDshake DELay time DELay MODE NONE LEADing TRAil...

Page 75: ...y MODE NONE LEADing TRAiling PULSe PARTial STRobe MODE POLarity POS NEG POLarity TRACe name VALue base value VALue FLAGn POLarity POS NEG POLarity HANDshaken DELay time DELay MODE NONE LEADing TRAiling PULSe PARTial STRobe MODE IOn TRACe CATalog DATA name block_data DATA name DEFine name size fill DEFine name DELete ALL NAME name ...

Page 76: ...ital CONTroln VALue SOURce DIGital FLAGn POLarity SOURce DIGital FLAGn POLarity RST Condition POLarity POSitive Example DIG CONT0 POL POS sets logical true to TTL high on port 0 control line DIGital CONTroln POLarity SOURce DIGital CONTroln POLarity returns a three character string either POS or NEG indicating the logical true condition of the control CTL line at port n Parameters Comments CONTrol...

Page 77: ...on Clears the control line i e sets the control line to logical 0 Example DIG CONT2 1 sets the 8 bit port 2 control line true DIGital CONTroln VALue SOURce DIGital CONTroln VALue reads the state of the control line on port n and returns a 0 or 1 indicating the logical condition of the CTL line Parameters Comments This command is only available when using the downloaded SCPI driver This command is ...

Page 78: ...last character of the keyword without spaces For 16 bit operations using WORD n must be 0 or 2 For 32 bit operations using LWORd n must be 0 The keyword LW32 may be used instead of LWORd when using the download version of the SCPI driver Related Commands SOURce DIGital DATAn POLarity SOURce DIGital DATAn VALue RST Condition All ports are set for data input Example DIG DATA3 BIT4 1 sets bit 4 the 5...

Page 79: ... data line register not the actual condition of the data lines The keyword LW32 may be used instead of LWORd when using the download version of the SCPI driver DATAn and BITm are the keywords used to write data to port n and bit m The port number n and bit number m must be the last character of the keyword without spaces For 16 bit operations using WORD n must be 0 or 2 For 32 bit operations using...

Page 80: ...DE NONE command ignores any programmed delay time For all other modes of handshaking 2µs is the minimum recommended Specific bands of delay settings are NOT allowed These are 0µs time 2µs 150µs time 200µs 15µs time 20µs 1 5ms time 2 0ms The controller uses a rounded up value for time if these values are specified The keyword LW32 may be used instead of LWORd when using the download version of the ...

Page 81: ...elay time between data output and the control line for data output at 32 bit port n and returns a decimal number between 0 and 015 Parameters Comments The delay time must be set to the same value on all ports used in a multiple port operation The keyword LW32 may be used instead of LWORd when using the download version of the SCPI driver DIG DATAn type HANDshake is the sequence used for commands r...

Page 82: ...be used instead of LWORd when using the downloaded version of the SCPI driver DIGital DATAn type HANDshake is the sequence used for commands relating to data handshaking at port n The port number n must be the last character of the keyword without spaces NONE deletes all automatic data handshaking between the Digital I O module and the peripheral For custom handshaking the control and the flag lin...

Page 83: ...oad version of the SCPI driver The handshake mode must be the same on all ports used in a multiple port operation This command will return one of the following strings NONE LEAD TRA PULS PART STR DATAn type HANDshake is the sequence used for commands relating to data handshaking at port n The port number n must be the last character of the keyword without spaces Related Commands SOURce DIGital CON...

Page 84: ...ce DIGital DATAn BITm SOURce DIGital DATAn POLarity SOURce DIGital DATAn VALue RST Condition POLarity POSitive Example DIG DATA0 POL POS sets logical true to TTL high on 8 bit port 0 data lines DIGital DATAn type POLarity SOURce DIGital DATAn BYTE POLarity returns a string either POS or NEG indicating the logical true condition of the data lines of 8 bit port n SOURce DIGital DATAn WORD POLarity r...

Page 85: ...shake Parameters Comments The keyword LW32 may be used instead of LWORd when using the download version of the SCPI driver DATAn and TRACe are the keywords used to write data to port n from block name The port number n must be the last character of the keyword without spaces Related Commands SOURce DIGital DATAn POLarity SOURce DIGital DATAn VALue RST Condition All ports are set for data input Exa...

Page 86: ...ctal or binary IEEE 488 2 specifies the following values for this parameter Decimal no parameter Hexadecimal H Octal Q Binary B DATAn is the keyword used for commands relating to data output at port n The port number n must be the last character of the keyword without spaces Related Commands SOURce DIGital DATAn BITm SOURce DIGital DATAn POLarity RST Condition All ports are set for data input Exam...

Page 87: ... using the downloaded SCPI driver The keyword LW32 may be used instead of LWORd when using the download version of the SCPI driver This command returns the programmed state of the data lines not the actual state of the data lines DATAn is the keyword used for commands relating to data output at port n The port number n must be the last character of the keyword without spaces Related Commands SOURc...

Page 88: ...Gital FLAGn POLarity RST Condition POLarity POSitive Example DIG FLAG0 POL POS sets logical true to TTL high on the port 0 flag line DIGital FLAGn POLarity SOURce DIGital FLAGn POLarity returns a string either POS or NEG indicating the logical true condition of the flag FLG line Parameters Example SOURCE DIGITAL FLAG0 POLARITY uses long commands to query the state of the logical true condition on ...

Page 89: ...IN sets a delay of 0 and is illegal for PULse and STRobe handshakes DIGital HANDshaken NONE command sets the delay to 0 For all other modes of handshaking 2µs is the minimum Specific bands of delay settings are NOT allowed These are 0µs time 2µs 150µs time 200µs 15µs time 20µs 1 5ms time 2 0ms The controller uses a rounded up value for time if these values are specified Related Commands SOURce DIG...

Page 90: ... the Digital I O module and a peripheral on 8 bit port n Handshakes are initiated by execution of a DIGital DATAn or MEASure DIGital DATAn command This form of the HANDshake command operates only on 8 bit ports Parameters Comments HANDshaken is the keyword used for commands relating to data handshaking at port n The 8 bit port number n must be the last character of the keyword without spaces NONE ...

Page 91: ...ital IOn SOURce DIGital IOn returns a 0 or 1 indicating the current condition of the I O line on port n Parameters Comments This command is only available when using the downloaded SCPI driver The I O line s polarity is fixed and is as follows When Digital I O module is programmed to output data the I O line is set low When Digital I O module is programmed to input data the I O line is set high IO...

Page 92: ...ents name must have been previously defined by a DIGital TRACe DEFine command The maximum length for name is 12 characters block_data is of the form digits length block where digits tells how many digits are used to define length length tells how many bytes are to be transferred in block block contains the actual data to transfer Example DIG TRAC DATA first_block 210ABCDEFGHIJ sends the data ABCDE...

Page 93: ...t parameter is absent the block is filled with zeros Parameters Comments The firmware can handle blocks with a total memory space of up to 12 Mbytes of memory space The actual amount available depends on the memory installed If the MEMory VME STATe ON command has been used this command will create blocks in the external add on memory If the MEMory VME STATe OFF command has been used this command w...

Page 94: ... ALL deletes all previously defined user memory data blocks Parameters None DIGital TRACe DELete NAME SOURce DIGital TRACe DELete NAME name deletes a previously defined user memory data block Parameters Comments name must have been previously defined by a DIGital TRACe DEFine command The maximum length for name is 12 characters Example DIG TRACe DEL first_block deletes a user memory block named fi...

Page 95: ... filter is enabled for that bit the same bit is set in the associated Event Register The contents of the Event Register and the enable mask are logically ANDed bit for bit if any bit of the result is set the summary bit for that register is set in the status byte The status byte summary bit for the Operation Status Register is bit 7 for the Questionable Signal Status Register bit 3 and for the Sta...

Page 96: ...igital I O module Parameters The non decimal numeric forms are the H Q or B formats specified by IEEE 488 2 OPERation ENABle STATus OPERation ENABle returns the mask set for the Operation Status Register This command does not affect the Agilent E1330 Digital I O module OPERation EVENt STATus OPERation EVENt returns the contents of the Operation Event Status Register Reading the register clears all...

Page 97: ...t Register and the unmasked bit s This command does not affect the Agilent E1330 Digital I O module Parameters The non decimal numeric forms are the H Q or B formats specified by IEEE 488 2 QUEStionable ENABle STATus QUEStionable ENABle returns the mask set for the Questionable Status Register This command does not affect the Agilent E1330 Digital I O module QUEStionable EVENt STATus QUEStionable ...

Page 98: ... Because each Digital I O module is a single instrument number is always 1 The command returns the following string Quad 8 bit Digital I O CTYPe SYSTem CTYPe number returns the module number and manufacturer Parameters Comments This command is only available when using the downloaded SCPI driver The command returns the following string revision number may vary and the serial number is always set t...

Page 99: ... a First In First Out manner by this command Comments Returns the error number and error string If no errors are in the error buffer returns 0 No error Related Commands ERR RST Condition None Example SYST ERR queries the mainframe for errors VERSion SYSTem VERsion returns the SCPI version to which this instrument complies Comments Returns a decimal value in the form YYYY R where YYYY is the year a...

Page 100: ... true CLS Clear status Clears all Event Registers the Request for OPC flag and all queues except output queue ESE mask Event status enable Sets the bits in the Event Status Enable Register ESE Event status enable query Queries the Event Status Enable Register ESR Event status register query Queries and clears the contents of the Standard Event Status Register SRE mask Service request enable Sets t...

Page 101: ...t m on port n after completion of handshake Reads port n after completion of handshake and stores block Reads bytes from port n after completion of handshake Assumes decimal format of input data Reads the port n FLAG line Returns 0 or 1 Used to implement custom handshakes MEMory DELete MACRo name VME ADDRess base address VME ADDRess MIN MAX VME SIZE base size VME SIZE MIN MAX VME STATe state VME S...

Page 102: ...SCPI driver only Sets delay between data output and assertion of control line for data output on port n Also sets strobe pulse for both output and input STRobe handshake Returns the time between data valid and assertion of control line to TRUE Selects type of handshake to transfer data between port n and peripheral Handshakes are initiated by execution of DIG DATAn or MEAS DIG DATAn commands Retur...

Page 103: ...tion ENABle OPERation EVENt PRESet QUEStionable CONDition QUEStionable ENABle mask QUEStionable ENABle QUEStionable EVENt Returns contents of Condition Register Sets mask for Enable Register Returns mask set in Enable Register Returns the contents of the Event Register Clears Enable Registers Returns contents of Condition Register Sets mask for Enable Register Returns mask set in Enable Register R...

Page 104: ...102 Agilent E1330B Digital I O Module Command Reference Chapter 5 Notes ...

Page 105: ...8 mA Vout Low 0 5 V Vin High 2 0 V 5 0 V Vin Low 0 8 V Iin High 2 5 mA 2 5 V Iin Low 3 2 mA 0 4 V Handshake Lines Iout High 250µA Vout High 5 V Iout Low 40 mA Vout Low 0 7 V Iout Low 16 mA Vout Low 0 4 V Vin High 2 0 V Vin Low 0 8 V Iin Low 1 75 mA Module Size Device Type B register based Connectors Used P1 Number of Slots 1 VXIbus Interface Capability Slave interrupter A16 D16 D08EO Interrupt Lev...

Page 106: ... Requirements Voltage 5 V Peak module current IPM A 0 50 Dynamic module current IDM A 0 01 Watts Slot 2 5 Cooling Slot 0 04 mm H20 0 21 liter sec Humidity 65 0º to 40ºC Operating Temperature 0º to 55ºC Storage Temperature 40º to 75ºC EMC RFI Safety meets FTZ 1046 1984 CSA 556B IEC 348 UL 1244 Net Weight kg 1 0 ...

Page 107: ...ion of A16 within a VXIbus master s memory map depends on the design of the VXIbus master you are using for the Agilent E1300 1301 Mainframe and Agilent E1405 E1406 Command Module the A16 space location starts at 1F000016 The A16 space is further divided so that the modules are addressed only at locations above 1FC00016 within A16 Further every module is allocated 64 register addresses 4016 The ad...

Page 108: ... E1405 06 Command Module is not part of your VXIbus system Figure B 1 the Agilent E1330 s base address is computed as 1 A16base C00016 LADDR 40 16 or decimal A16base 49 152 LADDR 64 where C00016 49 152 is the starting location of the register addresses LADDR is the module s logical address and 64 is the number of address bytes per VXI device For example the Agilent E1330 s factory set logical addr...

Page 109: ...6 or 2 080 768 LADDR 64 where 1FC00016 2 080 768 is the starting location of the VXI A16 addresses LADDR is the module s logical address and 64 is the number of address bytes per register based device Again the Agilent E1330 s factory set logical address is 144 If this address is not changed the module will have a base address of 1FC00016 90 40 16 1FC00016 240016 1FE40016 or 2 080 768 144 64 2 080...

Page 110: ...e select code word read or write READIO 8 Base_addr reg number WRITEIO 8 Base_addr reg number data Base_addr 1fc00016 LADDR 40 16 or 2 080 768 LADDR 64 offset register number Base_addr LADDR 256 reg number offset External Computer over GPIB to Agilent E1300 E1301 Mainframe or Agilent E1405 06 Command Module VXI READ logical_address offset VXI WRITE logical_address offset data DIAG PEEK Base_addr o...

Page 111: ...ilent E1330A B Quad 8 bit Digital I O module using its hardware registers The procedures for reading or writing to a register depend on your operating system and programming language Whatever the access method you will need to identify each register with its address These addresses are given in Table B 2 Table B 2 Register Map Register Name Address Manufacturer ID MSB 0016 Manufacturer ID LSB 0116...

Page 112: ...ers have been documented as 8 bit bytes If you access them using 16 bit transfers from a Motorola CPU the high and low byte will be swapped The Agilent E1300 01 Mainframe and Agilent E1405 06 Command Modules use Motorola CPUs Motorola CPUs place the highest weighted byte in the lower memory location and the lower weighted byte in the higher memory address Intel processors do just the opposite VXI ...

Page 113: ...his bit resets all Digital I O module components SR disables all output ports all ports become input ports and sets all other registers to default values Reads and writes to the other module registers will not transfer valid data when SR is asserted This bit is cleared by a hard reset IEN Main Interrupt Enable Writing a 1 to this bit allows interrupts from port controller ICs to assert interrupt o...

Page 114: ...sed IL0 and IL1 Interrupt Level Both bits must be left at 0 to initialize the Digital I O module for interrupt operation IP Interrupt Pending When equal to 1 indicates an interrupt is pending This is a read write bit You can force a hardware interrupt by setting this bit to 1 if PIEN is set to 1 and IEN is set to 1 in the Status Control Register PIEN Port Interrupt Enable When set to 1 enables int...

Page 115: ...port transfer interrupts specify the interrupt driven transfer mode of port refer to Port Handshake Register and set the interrupt enable bit bit 7 of Interrupt Control Register equal to 1 When the Port Data Register is read TI is set to 0 FI Forced Interrupt Is a read only bit When set to 1 indicates that a forced interrupt from the mainframe has occurred To force an interrupt write a 1 to bit 6 ...

Page 116: ... bit 1 However the current status of the PIR line does not indicate whether a peripheral interrupt has occurred Port peripheral interrupts are caused by transitions in the state of the PIR line Read bit 7 of the Port Transfer Control Register to determine whether a port peripheral interrupt has occurred Bits 2 and 3 Are not used FLG This is a read only bit Read this bit to find the normalized stat...

Page 117: ... controller To prevent incorrect handshaking due to interaction with other lines before enabling handshaking set the control line to FALSE Port Data Register The Port Data Register is a read write register It is used for both output and input Its operation depends on the state of the I O If I O is set for output bit 6 Port Transfer Control Register 0 data written to the Port Data Register is latch...

Page 118: ...ister Interrupt Driven the peripheral sets bit 1 of the Port Status Control Register and the Digital I O module interrupts the VXIbus for data transfer with the mainframe Fast Handshake the peripheral talks directly with the VXIbus s Data Acknowledge Line to transfer data between the Port Data Registers and the VXIbus Bits 2 and 3 Are not used EI Enable Inhibit This bit if set to 1 enables the STS...

Page 119: ...es no delay time For all output handshake types the delay period Td is equal to the range multiplier times the delay factor specified by bits 4 7 For example if you write the value 00010000 to register 5 the multiplier is 1ms and the delay factor is 1 If you write 11110010 to register 5 then the multiplier is 10µs and the delay factor is 15 hence the delay factor is 150µs The actual delay for a gi...

Page 120: ...es to the correct logic sense for your peripheral Positive true logic is the default You can invert a line by setting the appropriate bit equal to 1 Bits 0 3 Are not used IPIR Invert PIR This bit specifies the logic sense of a peripheral interrupt request If bit 4 0 a rising edge low to high transition of the PIR line triggers an interrupt If bit 4 1 a falling edge high to low transition of the PI...

Page 121: ...driven output procedure initiated by the computer The computer polls the Digital I O module to see if the data has been accepted by the peripheral by checking the Port Transfer Control Register bit 0 referred to as the acknowledge flag hence the name of flag driven Once the flag is TRUE the computer can output new data to the port The actual path followed by the peripheral and the Digital I O modu...

Page 122: ...en input procedure initiated by the computer The computer polls the Digital I O module to see if the data has been transmitted by the peripheral by checking the Port Transfer Control Register bit 0 referred to as the acknowledge flag hence the name flag driven Once the flag is TRUE the computer can read new data from the port The actual path followed by the peripheral and the Digital I O module to...

Page 123: ...the ID Device Type and Status Registers Writing an 8 bit Byte Writing a 16 bit Word Reading an 8 bit Byte Reading a 16 bit word Debugging Register Based Programs Using an Embedded Computer System Configuration The following example programs were developed with the module at logical address 144 The BASIC UX programs were developed using the Agilent E1300 Mainframe Series B BASIC language The C lang...

Page 124: ...s Control Register 30 Write a 0 then a 1 to bit 0 of status register 40 WRITEIO 9826 Base_addr Reg_addr 1 50 WRITEIO 9826 Base_addr Reg_addr 0 60 END C Version include stdio h include chpib h define LOG_ADDR 144 define BASE_ADDR long 0x1FC000 64 LOG_ADDR main int reg_addr float send_data 3 char state 2 13 10 send_data 0 BASE_ADDR reg_addr send_data 1 16 send_data 2 1 IOEOI 7L 0 IOEOL 7L 0 IOOUTPUT...

Page 125: ...ase_addr DVAL 1FE400 16 140 150 Map the A16 address space 160 170 CONTROL 16 25 2 used only with V360 Controller 180 Call the subprogram Read_regs 190 Read_regs Base_addr Reg_name Reg_addr 200 210 DATA Identification Register Device Register Status Register 220 DATA 00 02 04 230 END This subprogram steps through a loop that reads each register and prints its contents 320 SUB Read_regs Base_addr Re...

Page 126: ... IOOUTPUTS 70900L DIAG PEEK 11 IOEOI 7L 1 IOEOL 7L state 2 IOOUTPUTA 70900L send_data 2 IOENTER 70900L read printf nIdentification Register 0x read send_data 0 BASE_ADDR 2 IOEOI 7L 0 IOEOL 7L 0 IOOUTPUTS 70900L DIAG PEEK 11 IOEOI 7L 1 IOEOL 7L state 2 IOOUTPUTA 70900L send_data 2 IOENTER 70900L read printf nDevice Register 0x read send_data 0 BASE_ADDR 4 IOEOI 7L 0 IOEOL 7L 0 IOOUTPUTS 70900L DIAG...

Page 127: ...n transfer 60 WRITEIO 9826 Base_Addr DVAL 1D 16 00 70 Sets Port 1 Delay Register to 0 80 WRITEIO 9826 Base_Addr DVAL 21 16 00 90 Sets Port 1 Normalization Register polarity to positive true High true 100 WRITEIO 9826 Base_Addr DVAL 11 16 0 110 Sets Port 1 Status Control bit 6 to enable output 120 WRITEIO 9826 Base_Addr DVAL 0D 16 2 130 Sets Port 1 Transfer Control Register bit 1 to Enable Handshak...

Page 128: ...eg 0x0D data_reg 0x15 send_data 1 16 send_data 0 BASE_ADDR handshak_reg send_data 2 32 send_info state send_data send_data 0 BASE_ADDR delay_reg send_data 2 00 send_info state send_data send_data 0 BASE_ADDR normiz_reg send_data 2 00 send_info state send_data send_data 0 BASE_ADDR statuscont_reg send_data 2 00 send_info state send_data send_data 0 BASE_ADDR transfercont_reg send_data 2 2 send_info...

Page 129: ... 60 WRITEIO 9826 Base_Addr DVAL 1C 16 DVAL 0000 16 70 Sets Ports 0 1 Delay Register to 0 80 WRITEIO 9826 Base_Addr DVAL 20 16 DVAL 0000 16 90 Sets Ports 0 1 Normalization Register polarity to positive true 100 High true 110 WRITEIO 9826 Base_Addr DVAL 10 16 DVAL 0000 16 120 Sets Ports 0 1 Status Control bit 6 to enable output 130 WRITEIO 9826 Base_Addr DVAL 0C 16 DVAL 0202 16 140 Sets Ports 0 1 Tr...

Page 130: ...ge handshake and flag 50 driven transfer 60 WRITEIO 9826 Base_Addr DVAL 1D 16 00 70 Set Port 1 Delay Register to 0 80 WRITEIO 9826 Base_Addr DVAL 21 16 00 90 Set Port 1 Normalization Register polarity to positive true 100 High true 110 WRITEIO 9826 Base_Addr DVAL 11 16 64 120 Set Port 1 Status Control bit 6 to enable output 130 WRITEIO 9826 Base_Addr DVAL 0D 16 2 140 Set Port 1 Transfer Control Re...

Page 131: ...BASE_ADDR handshak_reg send_data 2 32 send_info state send_data send_data 0 BASE_ADDR delay_reg send_data 2 00 send_info state send_data send_data 0 BASE_ADDR normiz_reg send_data 2 00 send_info state send_data send_data 0 BASE_ADDR statuscont_reg send_data 2 00 send_info state send_data send_data 0 BASE_ADDR transfercont_reg send_data 2 2 send_info state send_data send_data 0 BASE_ADDR data_reg I...

Page 132: ...SIC s PAUSE STEP and CONT may now be used effectively to debug programs When a program does not seem to be proceeding correctly use PAUSE then STEP to trace the flow type variable names to see their value when PAUSEd and finally use CONT to proceed at full speed The main line of this program is the error handler It will catch all TIME OUTS and ERRORS that are not caught by lower level contexts Fiv...

Page 133: ...sing the RST command The following subprograms do register programming to the Agilent E1330 Reg_dump Prints the full register contents for debugging Enable_pir0 Enables pir0 to produce a interrupt Enable_pir1 Enables pir1 to produce a interrupt Enable_pir2 Enables pir2 to produce a interrupt Enable_pir3 Enables pir3 to produce a interrupt Enable_int A second level enable that allows PIR0 3 to reac...

Page 134: ...roduce a signal that can be wired to the PIR lines two register routines Res0_0 and Res0_1 were created and are called by pressing the defined Softkeys labeled Res0_0 and Res0_1 Res0_0 drives the Res0 line to 0 and Res0_1 drives the Res0 line high A pull up must also be attached to Res0 as it is an open collector device In order to test the PIR interrupts you connect a wire from Res0 pin 9 to one ...

Page 135: ...R A 360 UNTIL A 0 370 SUBEND 380 390 Main SUB Main This subroutine is treated as the main line 400 COM Instr Sys Dig 410 COM Register Logical_address 420 Put application code here 430 CLEAR Sys 440 OUTPUT Sys RST CLS OPC 450 ENTER Sys A 460 Logical_address 144 E1330 LOGICAL ADDRESS 470 CALL Reset_dig Reset the E1330 480 490 Now setup the system instrument to catch backplane interrupt on IRQ2 500 O...

Page 136: ...16 890 PRINT REGISTER D Reg H Hreg 3 4 VALUE D Query H Hquery 3 4 B Bquery 9 16 900 NEXT Reg 910 Reg_dump_ SUBEND 920 930 Int_ser SUB Intr_ser This is the interrupt service routine 940 COM Instr Sys Dig 950 PRINT got a interrupt 960 A SPOLL Sys Must serial poll to clear status byte 970 PRINT SERIAL POLL VALUE A 980 OUTPUT Sys STAT OPER EVEN Must read Operation Status register 990 ENTER Sys Stat_op...

Page 137: ...0 1370 COM Instr Sys Dig 1380 COM Register Logical_address 1390 Base 2031616 49152 Logical_address 64 1400 OUTPUT Sys DIAG POKE VAL Base DVAL 10 16 8 64 1410 PRINT STS0 DRIVEN TO 0 1420 Res0_0_ SUBEND 1430 1440 Enable_pir0 SUB Enable_pir0 1450 COM Instr Sys Dig 1460 COM Register Logical_address 1470 Base 2031616 49152 Logical_address 64 1480 OUTPUT Sys DIAG POKE VAL Base DVAL 0C 16 8 0 PI 0 1490 O...

Page 138: ... E1330 has several signal lines other than the data lines which can be individually controlled These lines are the FLG CTL STS RES and PIR lines The following BASIC language program demonstrates how to control these lines FLG0 FLG3 are input lines input from the peripheral to the Agilent E1330 module that can be used as individual input lines when not used as handshake lines The subroutine Ctl_flg...

Page 139: ...T ERRM 170 PRINT HERE IS THE E13XX ERROR STATUS 180 El3xx_errors 190 End END 200 210 SUB E13xx_errors This sub reads all errors from E13xx instruments 220 COM Sys Dvm Dig 230 DIM A 128 240 ABORT 7 250 CLEAR DVM 260 REPEAT 270 OUTPUT Dvm SYST ERR 280 ENTER Dvm A A 290 PRINT DVM ERROR A 300 UNTIL A 0 310 320 CLEAR Sys 330 REPEAT 340 OUTPUT Sys SYST ERR 350 ENTER Sys A A 360 PRINT SYSTEM ERROR A 370 ...

Page 140: ...STS0 740 COM Sys Dvm Dig 750 PRINT 760 PRINT SUBPROGRAM Res_sts_io 770 OUTPUT Dig RST RESET to power on state 780 Ladd 80 790 Base Start of A16 Offset to VXI Reg Offset to card Reg 800 Base 2031616 49152 Ladd 64 810 OUTPUT Sys DIAG POKE VAL Base DVAL 10 16 8 64 Drive RES0 to 0 820 OUTPUT Sys DIAG PEEK VAL Base DVAL 10 16 8 Read REG B 10H 830 ENTER Sys A 840 Bit0 BIT A 0 850 PRINT RES0 DRIVEN TO 0 ...

Page 141: ...ST RESET to power on state 1220 Ladd 80 1230 Base Start of A16 Offset to VXI Reg Offset to card Reg 1240 Base 2031616 49152 Ladd 64 1270 OUTPUT Sys DIAG POKE VAL Base DVAL 08 16 8 131 Set PIEN 1 1280 OUTPUT Sys DIAG POKE VAL Base DVAL 0C 16 8 128 Set PI 1 1290 OUTPUT Sys DIAG POKE VAL Base DVAL 10 16 8 64 Drive RES0 to 0 1300 OUTPUT Sys DIAG PEEK VAL Base DVAL 10 16 8 Read REG B 10H 1310 ENTER Sys...

Page 142: ...port_xfr_3 0x0F define port_ctl_0 0x10 define port_ctl_1 0x11 define port_ctl_2 0x12 define port_ctl_3 0x13 define port_data_0 0x14 define port_data_1 0x15 define port_data_2 0x16 define port_data_3 0x17 define port_hand_0 0x18 define port_hand_1 0x19 define port_hand_2 0x1A define port_hand_3 0x1B define port_del_0 0x1C define port_del_1 0x1D define port_del_2 0x1E define port_del_3 0x1F define p...

Page 143: ... 0 NULL if base_addr NULL errnum igeterrno printf imap failure error d s n errnum igeterrstr errnum exit 1 perform a soft reset iwpoke base_addr card_stat 0xFCBF iwpoke base_addr card_stat 0xFCBE read MFR and device ID registers data_word iwpeek base_addr mfr_id printf MFR ID value 04X n data_word data_word iwpeek base_addr dev_id printf Dev ID value 04X n data_word output data bytes to ports 0 an...

Page 144: ... ibpoke base_addr port_del_2 0x00 ibpoke base_addr port_norm_2 0x00 ibpoke base_addr port_ctl_2 0x40 ibpoke base_addr port_xfr_2 0x00 data_byte ibpeek base_addr port_data_2 printf port data register value 02X n data_byte input a data byte at port 1 leading edge handshake ibpoke base_addr port_hand_1 0x20 ibpoke base_addr port_del_1 0xF2 ibpoke base_addr port_norm_1 0x00 ibpoke base_addr port_ctl_1...

Page 145: ...l asserted when in a handshake mode other than NONE 222 Data out of range Value specified is out of the legal range for parameter 224 Illegal Parameter Value Inconsistent parameter value or block not found 240 Hardware Error Hardware error detected during power on cycle Return Digital I O Module to Agilent Technologies for repair 410 Query Interrupted Data is not read from the output buffer before...

Page 146: ...144 Error Messages Appendix C Notes ...

Page 147: ...l switch 18 31 module 31 primary 31 registers 105 110 secondary 31 Address continued space defined 68 105 switch setting 18 31 VME memory 69 Algorithm input register based 120 output register based 119 B Base Address 106 107 Binary Format 52 54 BIT input 35 50 numbers 50 51 54 output 36 51 querying 77 specifying 50 51 76 summary bit 93 95 Boolean Command Parameters 59 BYTE bit designations 12 bit ...

Page 148: ...system 72 92 STATus subsystem 93 95 SYSTem subsystem 96 97 Commands abbreviated 58 IEEE 488 2 57 98 implied 14 58 keyword substitutions 59 linking 59 optional 14 58 optional parameters 14 59 parameters 59 quick reference 99 101 SCPI 57 99 101 format 14 57 59 Commands continued separator 58 types 57 Common Commands 57 98 CLS 98 DMC 68 98 EMC 98 EMC 98 ESE 98 ESE 98 ESR 98 GMC 98 IDN 98 LMC 98 OPC 9...

Page 149: ...te 33 43 description 41 invert DATA 118 mapping 12 numbers 50 51 54 open collector 28 29 polarity 33 41 43 82 Data Lines continued ports 41 pull up 19 28 setting polarity 82 specify logic sense 118 termination 19 TTL levels 52 Debugging Programs 130 Decimal Format 52 Default and Reset States 33 43 Deleting automatic data handshaking 88 macros 68 memory data blocks 92 Device Identification Register...

Page 150: ...34 44 49 80 88 STRobe mode 34 44 49 78 80 81 87 89 117 timing 34 44 49 78 79 87 88 TRAiling edge mode 34 44 46 80 81 88 89 117 types of 116 Handshake continued using CTL line 54 using FLG line 54 86 with peripheral 21 80 88 Header Connector 25 Hexadecimal Format 52 54 IBASIC Examples reading an 8 bit byte 128 registers 123 resetting the module 122 using non data I O lines 136 PIR interrupt lines 1...

Page 151: ... DIGital DATAn BYTE BITm 64 BYTE TRACe 65 BYTE VALue 66 LWORd BITm 64 LWORd TRACe 65 LWORd VALue 66 type BITm 15 64 type TRACe 65 type VALue 37 50 53 66 WORD BITm 64 WORD TRACe 65 WORD VALue 66 MEASure DIGital FLAGn 67 Memory add on VME 69 catalog mainframe system 90 catalog VME blocks 90 define user block 91 delete blocks from 92 disable enable VME 71 external VME 68 71 query block size 92 query ...

Page 152: ...d algorithm 119 using open collector 28 P Parameters 59 PARTial Handshake Mode 34 44 48 80 81 88 89 117 Peripheral connecting to computers 26 27 GPIO connecting to 26 27 handshake 21 80 88 interrupt 22 bus 20 interrupts 114 pinout 22 23 reset 22 Peripheral Control Line See PIR Control Line Pinouts connectors 24 peripheral 22 23 PIR Control Line 12 22 description 43 interrupts 131 operation 43 oper...

Page 153: ...up calculating resistor value 28 discrete resistive 29 enable jumpers 19 external 28 29 internal 19 29 resistor 19 28 PULSe Handshake Mode 34 44 47 78 80 81 87 89 117 Q Query data bits 77 blocks available 90 lines polarity 82 error register 97 external memory state 71 flag line polarity 86 status 67 handshake delay time 79 88 mode 81 89 I O control line 89 memory block size 92 module description 9...

Page 154: ...ription 43 operation 43 operation of 114 status 114 using as output lines 136 Reset Control Line See RES Control Line Reset States 33 43 109 Resetting Module 122 Ribbon Cable connecting 25 pins 24 25 replacement 12 RMC 98 RST 33 43 98 S SAV 98 SCPI drivers downloading 13 status registers 93 version query 97 SCPI Commands 57 99 101 abbreviated 58 abbreviated commands 58 command separator 58 DISPlay...

Page 155: ...80 type HANDshake MODE 81 type POLarity 82 type POLarity 82 type TRACe 83 type VALue 14 52 84 type VALue 85 SOURce DIGital DATAn continued WORD BITm 76 WORD BITm 77 WORD HANDshake DELay 78 WORD HANDshake DELay 79 WORD HANDshake MODE 80 WORD HANDshake MODE 81 WORD POLarity 82 WORD POLarity 82 WORD TRACe 83 WORD VALue 84 WORD VALue 85 SOURce DIGital FLAGn POLarity 33 43 86 POLarity 86 SOURce DIGital...

Page 156: ...117 Transfer Mode 116 Transition Filters 93 TRG 98 TST 98 type keyword described 37 53 substitutions 37 53 59 64 66 76 85 port combinations allowed 55 Typical Driver Receiver Connection 29 U Understanding the Agilent E1330B 41 54 Using external pull ups 28 handshake mode 44 49 80 81 88 the Agilent E1330B 31 39 trace memory 38 39 83 V VMEbus 11 68 add on VME memory 69 catalog memory 90 external mem...

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