SOM-5893 User Manual
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Chipset........................................................................................ 34
Figure 3.24Chipset Setup........................................................... 34
Figure 3.25PCH-IO Configuration .............................................. 35
Figure 3.26South Bridge............................................................. 36
Figure 3.27SB SATA Configuration............................................ 37
Figure 3.28SB USB Configuration.............................................. 38
Figure 3.29SB SD Configuration ................................................ 39
Figure 3.30SB GPP Port Configuration ...................................... 40
Figure 3.31SB HD Azalia Configuration ..................................... 41
Figure 3.32North Bridge ............................................................. 42
Figure 3.33Memory configuration............................................... 43
Figure 3.34Socket 0 information................................................. 44
Boot Settings .............................................................................. 45
Figure 3.35Boot Setup Utility...................................................... 45
Figure 3.36CSM16 parameters .................................................. 46
Figure 3.37CSM parameters ...................................................... 47
S/W Introduction and Installation
.... 51
Windows 7 Driver Setup ............................................................. 52
Other OSs................................................................................... 52
................................. 55
SOM-5893 Type 6 Pin Assignments....................................................... 56
................................ 61
Programming the Watchdog Timer ......................................................... 62
........................... 63
........................ 65
Table D.1: System I/O ports....................................................... 66
DMA Channel Assignments .................................................................... 68
Table D.2: DMA channel assignments....................................... 68
Table D.3: Interrupt assignments............................................... 68
1st MB Memory Map............................................................................... 69
Table D.4: 1st MB Memory Map ................................................ 69