Advantech SOM 144, Design Specification

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10 SOM 144 Design Specification Rev.1.0
PIDE_CS3# Primary IDE Chip Select 3 for Channel 1. This com-
mand output pin enables the IDE device to watch
the Read/Write Command.
PIDE_DRQ IDE DMA Request for IDE Master. This is the in-
put pin from the IDE DMA request to do the IDE
Master Transfer. It will active high in DMA or Ul-
tra-33 mode and always be inactive low in PIO mode.
PIDED_AK# IDE DACK# for IDE Master. This is the output pin
to grant the IDE DMA request to begin the IDE
Master Transfer in DMA or Ultra-33 mode.
PIDE_RDY IDE Ready. This is the input pin from the IDE Chan-
nel to indicate the IDE device is ready to terminate
the IDE command in PIO mode. The IDE device can
de-assert this input (logic 0) to expand the IDE com-
mand if the device is not ready. In Ultra-33 mode,
this pin has different functions. In read cycle, IDE
device will drive this signal as Data Strobe
(DSTROBE) to use by IDE Busmaster to strobe the
input data. In write cycles, this pin is used by IDE
device to notify IDE Busmaster as DMA Ready
(DDMARDY#).
PIDE_IOR#
IDE IOR# Command. This is the IOR# command
output pin to notify the IDE device to assert the
Read Data in PIO and DMA mode. In Ultra-33
mode, this pin has different function. In read
cycle, this pin is used by IDE Busmaster to notify
IDE device as DMA Ready (DDMARDY#). In
write cycle, IDE Busmaster will drive this signal
as Data Strobe (DSTROBE) to use by IDE device
to strobe the output data.
PIDE_IOW# IDE IOW# Command. This is the IOW# command
output pin to notify the IDE device that the avail-
able Write Data is already asserted by IDE Bus-
master in PIO and DMA mode. In Ultra-33 mode,
this pin is driven by IDE Busmaster to force IDE