Advantech SOM 144, Design Specification

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8 SOM 144 Design Specification Rev.1.0
3.1 144 pin SODIMM (PCI/IDE/ Serial port
/USB/AC97/KB/Mouse)
GND Ground.
VCC +5V +/- 5% power supply.
RESERVED Reserved pin.
3.1.1 PCI
All signals are 3.3 V level PCI signals. All pullups are integrated on
the SOM 144 Module.
PCICLK1..3 PCI clock outputs for 3 external PCI devices.
REQ#0..2 Bus Request signals of 3 external PCI Masters.
When asserted, it means the PCI Master is request-
ing the PCI bus ownership from the arbiter. Please
refer the specification for your SOM 144 Module
for used/ unused PCI Masters and shared PCI
Masters with onboard devices.
GNT#0..2 Grant signals to PCI Masters. When asserted by
the arbiter, it means the PCI master has been legally
granted to own the PCI bus.
AD0..31 PCI Address and Data Bus Lines. These lines are
connected to the PCI bus. AD[31:0] contain the
information of address or data for PCI transactions.
CBE#0..3 PCI Bus Command and Byte Enables. Bus com-
mands and byte enables are multiplexed in these
lines for address and data phases, respectively.
PAR Parity bit of PCI bus. It is the even parity bit across
PAD[31:0] and CBE#[3:0].
SERR# System Error or PCI Clock RUN. The Northbridge
asserts SERR# if parity errors are detected in
DRAM.
GPERR# Parity Error. For PCI operation per exception grant-
ed by PCI 2.1 specification.