Advantech SOM 144, Design Specification

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Chapter 3 Signal Description 9
LOCK# Lock Resource Signal. This pin indicates the PCI
master or the bridge intends to do exclusive trans-
fers.
DEVSEL# Device Select. When the target device has decod-
ed the address as its own cycle, it will assert
DEVSEL#.
TRDY# Target Ready. This pin indicates the target is ready
to complete the current data phase of transaction.
IRDY# Initiator Ready. This signal indicates the initiator is
ready to complete the current data phase of trans-
action.
STOP# Stop. This signal indicates the target is requesting
the master to stop the current transaction.
FRAME# Cycle Frame of PCI Buses. This indicates the be-
ginning and duration of a PCI access. It will be as
an output driven by Northbridge on behalf of CPU,
or as an input during PCI master access.
PCIRST# PCI Bus Reset. This is an output signal to reset the
entire PCI Bus. This signal will be asserted during
system reset and is a logic invert of RSTDRV.
IRQW, IRQX, IRQY, IRQZ
PCI interrupts from CPU-PCI bridge.
For further descriptions of PCI signals please refer to Chapter 4.
3.1.2 IDE
All required pullups are integrated on the SOM 144 Module. ESD and
EMV protection devices need to be integrated on the backplane.
PIDE_D0..15 Primary/ Secondary IDE ATA Data Bus. These are
the Data pins connected to Primary Channel.
PIDE_A0..2 IDE ATA Address Bus. These are the Address pins
connected to Secondary Channel.
PIDE_CS1# Primary IDE Chip Select 1 for Channel 0. This com-
mand output pin enables the IDE device to watch
the Read/Write Command.