Advantech PCLS-848-P, User Manual

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CHAPTER 2 INSTALLATION 69
Demand-transfer mode and Cascade mode are not supported by this interface.
The IEEE-488 interface disables the auto-initialization function and uses only the
address register increment direction on the 8237 chip because of the natUre of IEEE-
488 bus data transfer.
Bit 14 of <setting> of the icinit( ) procedure determines the DMA: operating mode.
Setting the bit to “0” lets the DMA operate in single-byte-transfer mode for low
DMArate and high CPU through put. Setting the bit to “1” lets the DMA operate in
block-transfer mode for high DMArate and low CPU throughput.
Bit 15 of <setting> of ieinit( ) procedure determines the sequence of software to
handle a DMA. When bit 15 is set to “0”, the software waits for the completion of
DMAbefore it goes further. When bit 15 is set to “1”, the software initializes the
DMAand then goes away. It is also called BACKGROUNDoperation. When data
transfer is timing related with the software, background operation cannot be used.
The IEEE-488 interface DMA is quite transparent to users. Once you select the
DMA mode by calling icinit( ) procedure, all further data transfer proceeds in this
mode. However, when you select block-transfer mode, the DMAchannel 0 memory
refresh may be held ~ long enough to corrupt RAM memory content. Do not use
block transfer mode unless you have confidence that the data transfer will be
completed within the time limits of memory refresh.
When using background operation, the CPU does not care about the data transfer. The
data string can be terminated by byte count only. The data format problem then must
be handled by users. It is safe to use DMA in single-byte-transfer and non-back-
ground operation mode (the default condition). The other modes can be used only
when you have solid understanding of the PC, 8237 DMA chip and your IEEE-488
devices. We do not recommend using this mode.
5.2. Transfer Speed
The data transfer speed is determined by several factors: