Advantech PCL-832, Manual

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52 PCL-832 User's Manual
B A S E + 0 2
R e a d CH1 Status
Base + 02: Register Layout (Read)
D15 ~ D4 D 3 D 2 D 1 D 0
N/A E - O V N / A I n d e x H o m e
E-OV : The Error counter overflow status
0 : An overflow has occurred
1 : An overflow has not occurred
INDEX : The index input status
0 : The index input is LOW
1 : The index input is HIGH
HOME : The home input status
0 : The home input is HIGH
1 : The home input is LOW
W r i t e CH1 Scaling Gain
Base + 02: Register Layout (Write)
D15 ~ D8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
N/A N / A N / A S 5 S 4 S 3 S 2 S 1 S 0
S5 ~ S0 : The Scaling Gain value
B A S E + 0 4
W r i t e The DDA cycle time multiplier
Base + 04: Register Layout (Write)
D 1 5 ~ D 1 2 D11 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
N / A F11 F 1 0 F 9 F 8 F 7 F 6 F 5 F 4 F 3 F 2 F1 F 0
F11 ~ F0 : The DDA cycle time value
DDA cycle time = 0.512ms * Register value (F11~F0)