Advantech PCL-832, Manual

Page: 23 / 63

Chapter 3 Operation 19
summing circuit will be anti-clockwise (-).
This signal is again fed to the error-counter, through the gain circuit,
which causes the error-counter to be decremented/incremented
(depending on the direction). If the whole operation was successful,
the error counter will therefore have a zero value at completion of the
pulse/motion.
It the motor does NOT respond, no signal is fed back to the summing
circuit, the error counter does not decrement, and a voltage will still
be output on the DAC. When the next pulse reaches the error counter
(through all the steps discussed), it will increment the value once
again. The output voltage on the DAC will therefore be higher,
prompting the servo motor (or perhaps the servo driver) to respond.
When the error counter reaches its maximum limit, 4095, it means
that there is a problem with the servo motor, the servo motor driver or
the encoder on the servo motor. Operation will be halted at this stage,
and the PCL-832 will have to be reset before normal operation can
continue.
The DDA cycle time
As previously discussed, the DDA cycle time refers to the time that
elapses between the starting of the pulse sequence, and the completion
of pulse output (for that cycle). To ensure synchronization between all
three channels, one DDA cycle time is used for all three channels.
To calculate the DDA cycle time you use the following formula :
DDA cycle time = 0.512ms x Register value (BASE + 04)
The register value referenced above can be set from 2 to 4094 (in
steps of 2) by writing the value into the register's address (or using one
of the library functions to do that). This means that the DDA cycle
time can be set from 1ms to 2 seconds. Remember that you have to set
up the DDA pulse buffer (with the next DDA cycle's no. of pulses)
before the completion of the current DDA cycle.