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User's Note for PCLD-818L Revision A2 Card

The purpose of this 'User's Note' is to inform you of the new jumper
settings on the PCL-818L revised A2 card. If your PCL-818L card is
revision A1, this note will not apply to you.

The revision change is to simplify the multiplexing capability of the
PCL-818L. With the new jumpers onboard, JP8, JP9, JP10 and JP11,
you can select which cable controls the daughter boards connected.
This is done via either the D-type 37-pin connector or the original
20-pin connector. These cables, CN1 and CN3, use digital control
signal outputs D0 to D3. Please contact your distributor to find out
exactly which daughter boards can support this special feature.

To connect daughter boards without this function, set the jumpers to
the 'D' side (left hand side). With this configuration the digital
signals D0 to D3 will be on the 20-pin connector CN1. This is the
standard setup for the PCL-818L revision A1.

The default jumper setting on the PCL-818L revision A2 is with the
jumpers set to the 'S' (right hand side). In this configuration, the
digital output signals D0 to D3 will be on the 37-pin connector CN3.
The signal pins on CN1 will now be floating.

D0

D1

D2

D3

S0

S1

S2

S3

JP8 to JP11

Digital Output

to CN3 (37-pin)

JP8 to JP11

Digital Output

to CN1 (20-pin)

D0

D1

D2

D3

S0

S1

S2

S3

Default

Connector CN3

Pin Assignments

Connector

CN1 Pin

Assignments

Jumper

Configuration

1

3

5

7

9

1 1

1 3

1 5

1 7

1 9

2

4

6

8

1 0

1 2

1 4

1 6

1 8

2 0

D / O 0

D / O 2

D / O 4

D / O 6

D / O 8

D / O 1 0

D / O 1 2

D / O 1 4

D . G N D

+ 5 V

D / O 1

D / O 3

D / O 5

D / O 7

D / O 9

D / O 1 1

D / O 1 3

D / O 1 5

D . G N D

+ 1 2 V

2

1

4

5

6

7

8

9

10

11

12

13

15

16

14

17

18

19

20

21

3

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

A / D H 0

A / D H 1

A / D H 2

A / D H 3

A / D H 4

A / D H 5

A / D H 6

A / D H 7

A . G N D

A . G N D

V R E F

S 0

+ 1 2 V

S 2

D . G N D

N C

C O U N T E R 0 C L K

C O U N T E R 0 O U T

+ 5 V

A / D L 0

A / D L 1

A / D L 2

A / D L 3

A / D L 4

A / D L 5

A / D L 6

A / D L 7

A . G N D

A . G N D

D A 0 O U T

D A 0 V R E F I N

S 1

S 3

D G N D

T R I G 0

C O U N T E R 0 G A T E

P A C E R

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Summary of Contents for PCL-818L

Page 1: ...PCL 818L High performance DAS card with programmable gain ...

Page 2: ... Co Ltd Information provided in this manual is intended to be accurate and reliable However Advantech Co Ltd assumes no responsibility for its use nor for any infringe ments of the rights of third parties which may result from its use Acknowledgments PC LabCard is a trademark of Advantech Co Ltd IBM and PC are trademarks of International Business Machines Corporation MS DOS Microsoft C and QuickBA...

Page 3: ...ions 21 Analog input connections 22 Expanding analog inputs 24 Analog output connection 25 Digital signal connections 25 Chapter 4 Register structure and format 27 A D data registers BASE 0 1 29 Software A D trigger BASE 0 29 A D range control BASE 1 30 MUX scan register BASE 2 30 Digital I O registers BASE 3 11 32 D A output registers BASE 4 5 32 A D status register BASE 8 33 Control register BAS...

Page 4: ...ut and output 47 Chapter 8 Programmable timer counter 49 The Intel 8254 50 Counter read write and control registers 50 Counter operating modes 53 Counter operations 55 Counter applications 56 Chapter 9 Direct memory access operation 57 Using DMA transfer with the PCL 818L 59 Appendix A Block Diagram 61 Appendix B Connector switch and VR Locations 63 Appendix C PC I O port address map 65 Appendix D...

Page 5: ...Chapter 1 General information 1 1 General information C H A P T E R ...

Page 6: ...ing half size card is fully software compatible with the PCL 818 This puts rich software support and a wide variety of external signal conditioning boards at your disposal The PCL 818L is excellent for data acquisition process control automatic testing and factory automation Features 16 single ended or eight differential analog inputs switch selectable 12 bit A D up to 40 KHz sampling rate with DM...

Page 7: ...f reading 1 bit Linearity 1 bit Trigger mode Software trigger on board programmable pacer trigger or external trigger Ext trigger TTL compatible Load is 0 4 mA max at 0 5 V and 0 05 mA max at 2 7 V Data transfer Program interrupt or DMA å Analog output D A converter Channels 1 channel Resolution 12 bits Output range 0 to 5 10 V with on board 5 10 V reference Max 10 V with external DC or AC referen...

Page 8: ...54 or equivalent Counters 3 channels 16 bit 2 channels are permanently configured as programmable pacers 1 channel is free for your applications Input gate TTL CMOS compatible Time base Pacer channel 1 10 MHz or 1 MHz switch selectable Pacer channel 2 Takes input from channel 1 Pacer channel 0 Internal 100 KHz or external clock 10 MHz max Source selected with Timer Counter Enable Register BASE 10 ...

Page 9: ...emp 0 to 50o C Storage temp 20 to 65o C Daughterboards We offer a wide variety of optional daughterboards to help you get the most from your PCL 818L You will need the PCLD 774 Analog Expansion Board or PCLD 8115 Wiring Terminal Board to make connections å PCLD 789 Amplifier Multiplexer board This analog input signal conditioning board multiplexes up to 16 differential inputs to one A D input chan...

Page 10: ...d a cable to connect to the PCL 818L s digital input ports å PCLD 779 8 channel relay isolated multiplexer and amplifier board This board lets you easily make multi channel temperature measure ments We designed it for the cost sensitive customer who requires precision low level signal measurement and isolation for industrial applications å PCLD 770 with PCLD 7701 and PCLD 7702 modules PCLD 770 acc...

Page 11: ... data analysis and digital signal processing DSP Development Corp å LABTECH NOTEBOOK Integrated data acquisition software with real time analysis display and process control Laboratory Technologies Corp å LABTECH ACQUIRE Low cost data acquisition software Laboratory Technologies Corp å DAXpert 1 0 DOS based general purpose data acquisition package You can quickly set up an experiment acquire data ...

Page 12: ...Data Corporation å GENESIS Icon based process control software for graphically creating simulat ing and executing real time data acquisition and process control strategies ICONICS Inc å PC Streamer A menu driven user friendly data acquisition software package capable of continuously streaming up to 16 channels of acquired data to disk It can store at up to 200 KB sec with no limitations on file si...

Page 13: ...Chapter 2 Installation 9 C H A P T E R 2 Installation ...

Page 14: ... metal panel Handle the card only by its edges to avoid static electric discharge which could damage its integrated circuits Keep the antistatic package Whenever you remove the card from the PC please store the card in this package for protection You should also avoid contact with materials that hold static electricity such as plastic vinyl and styrofoam Switch and jumper settings We designed the ...

Page 15: ... 01F l l l l l 200 20F l l l l l 210 21F l l l l 300 30F l l l l 3F0 3FF Off l On default Note Switches 1 6 control the PC bus address lines as follows Switch 1 2 3 4 5 6 Line A9 A8 A7 A6 A5 A4 Appendix C provides a PC I O port address map to help you avoid the I O addresses for standard PC devices DMA Channel Selection JP1 The PCL 818L supports DMA data transfer Jumper JP1 selects the DMA channel...

Page 16: ...in the 8254 See Chapter for more information on the card s 8254 counter timer 10 MHz 1 MHz default TRIG0 and GATE0 Selection JP3 JP3 has two jumpers The upper jumper selects the card s A D trigger source when you use external triggering The lower jumper selects the gate control for counter 0 of the card s 8254 timer counter Upper jumper source for external trigger You have two choices DI0 pin 1 on...

Page 17: ...10 V With JP4 set to INT the D A channel has an output range of 0 V to 5 V or 0 V to 10 V When you set JP4 to EXT the D A converter takes its reference voltage input from pin 31 of connector CN3 You can apply any voltage between 10 V and 10 V to this pin to function as the external reference The reference input can be either DC or AC 100 KHz When you use an external reference with voltage Vref you...

Page 18: ...ntial analog input channels Jumper JP6 switches the channels between single ended or differential input as shown below 16 S E inputs Eight differential inputs default Input voltage range 5 or 10 V JP7 Jumper JP7 selects the input voltage range for the A D converter When you set JP7 to 5 V the maximum input voltage range is 5 V and the programmable input ranges are 5 V 2 5 V 1 25 V and 0 625 V When...

Page 19: ...l come out on connector CN3 37 pin These four digital output signals select the analog input channel when you use a multiplexer amplifier daughterboard Daughterboards with a DB 37 connector such as the PCLD 789D or PCLD 779D read the digital output signals from the DB 37 connector DN3 With other daughterboards you will need to connect an external 20 pin flat cable from CN1 to the daughterboard Set...

Page 20: ...round D A Analog output D O Digital output D I Digital input D GND Digital and power supply ground CLK Clock input for the 8254 GATE Gate input for the 8254 OUT Signal output of the 8254 VREF Internal voltage reference VREFIN External voltage reference input å Connector CN1 Digital output D O 0 1 2 D O 1 D O 2 3 4 D O 3 D O 4 5 6 D O 5 D O 6 7 8 D O 7 D O 8 9 10 D O 9 D O 10 11 12 D O 11 D O 12 13...

Page 21: ...DS1 2 A DS2 3 A DS3 4 A DS4 5 A DS5 6 A DS6 7 A DS7 8 AGND 9 AGND 10 V REF 11 S0 12 12 V 13 S2 14 DGND 15 NC 16 COUNTER 0 CLK 17 COUNTER 0 OUT 18 5 V 19 20 A DS8 21 A DS9 22 A DS10 23 A DS11 24 A DS12 25 A DS13 26 A DS14 27 A DS15 28 AGND 29 AGND 30 DA0 OUT 31 DA0 VREFIN 32 S1 33 S3 34 DGND 35 TRIG0 36 COUNTER 0 GATE 37 PACER Note Jumpers JP8 to JP11 select the output connector either CN1 or CN3 f...

Page 22: ...4 DGND 15 NC 16 COUNTER 0 CLK 17 COUNTER 0 OUT 18 5 V 19 20 A DL0 21 A DL1 22 A DL2 23 A DL3 24 A DL4 25 A DL5 26 A DL6 27 A DL7 28 AGND 29 AGND 30 DA0OUT 31 DA0VREFIN 32 S1 33 S3 34 DGND 35 TRIG0 36 COUNTER 0 GATE 37 PACER Note Jumpers JP8 to JP11 select the output connector either CN1 or CN3 for digital output signals 0 to 3 If you switch the output to CN1 no signals will appear on CN3 and vice ...

Page 23: ...lot 5 Remove the screw that secures the expansion slot cover to the system unit Save the screw to secure the interface card retaining bracket 6 Carefully grasp the upper edge of the PCL 818L card Align the hole in the retaining bracket with the hole on top of the expansion slot and align the gold striped edge connector with the expansion slot socket Press the board firmly into the socket 7 Secure ...

Page 24: ...egister programming The driver supports the following languages BASICA GWBASIC QUICK BASIC Microsoft C C and PASCAL Turbo C C Borland C C and Turbo PASCAL Please refer to the Software Driver User s Manual for more information 2 Demonstration programs 3 A calibration program 4 A test programs We strongly recommend that you make a working copy from the master disk and store the master disk in a safe...

Page 25: ...Chapter 3 Signal connections 21 3 Signal connections C H A P T E R ...

Page 26: ... ended and differential input connections is the number of signal wires per input channel Single ended channel connections Single ended connections use only one signal wire per channel The voltage on the line references to the common ground on the card A signal source without a local ground is called a floating source It is fairly simple to connect a single ended channel to a floating signal sourc...

Page 27: ...urn of the equipment and building wiring The difference between the ground voltages forms a common mode voltage To avoid the ground loop noise effect caused by common mode voltages connect the signal ground to the LOW input Do not connect the LOW input to the PCL 818L ground directly In some cases you may also need a wire connection between the PCL 818L ground and the signal source ground for bett...

Page 28: ...terboards such as PCLD 779 and PCLD 789 It features five sets of on board 20 pin header connectors A special star type architecture lets you cascade multiple signal conditioning boards without the signal attenuation and current loading problems of normal cascading The PCLD 8115 Screw Terminal Board makes wiring connections easy It provides 20 pin flat cable and DB 37 cable connectors It also inclu...

Page 29: ...ent for D A outputs should not exceed 5 mA Connector CN3 provides D A A D and counter signals Important D A signal connections such as input reference D A outputs and analog ground appear below Digital signal connections The PCL 818L has 16 digital input and 16 digital output channels The digital I O levels are TTL compatible The following figure shows connections to exchange digital signals with ...

Page 30: ... 818L User s Manual D GND 4 7K 5V To receive an OPEN SHORT signal from a switch or relay add a pull up resistor to ensure that the input is held at a high level when the contacts are open See the figure below ...

Page 31: ...Chapter 4 Register structure and format 27 4 Register structure and format C H A P T E R ...

Page 32: ... of each of the card s registers I O port address map The following table shows the function of each register or driver and its address relative to the card s base address I O port address assignments Address Read Write BASE 0 A D low byte channel Software A D trigger BASE 1 A D high byte A D range control BASE 2 MUX scan channel MUX scan channel range control pointer BASE 3 D I low byte DI0 7 D O...

Page 33: ...ead only A D high byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Value AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD11 to AD0 Analog to digital data AD0 is the least significant bit LSB of the A D data and AD11 is the most significant bit MSB C3 to C0 A D channel number from which the data is derived C3 is the MSB and C0 is the LSB Software A D trigger BASE 0 You can trigger an A D conversion from software the card s on...

Page 34: ...BASE 1 write only A D range control code Bit D7 D6 D5 D4 D3 D2 D1 D0 Value N A N A N A N A N A N A G1 G0 Range codes and JP7 settings appear below Input range Range code JP7 5 V JP7 10 V G1 G0 5 V 10 V 0 0 2 5 V 5 V 0 1 1 25 V 2 5 V 1 0 0 625 V 1 25 V 1 1 MUX scan register BASE 2 Read write register BASE 2 controls multiplexer MUX scanning The high nibble provides the stop scan channel number and ...

Page 35: ...Start scan channel number The MUX scan register low nibble CL3 to CL0 also acts as a pointer when you program the A D input range see previous section When you set the MUX start channel to N the range code written to the register BASE 1 is for channel N Programming example This BASIC code fragment sets the range for channel 5 to 0 625 V 200 OUT BASE 2 5 SET POINTER TO CH 5 210 OUT BASE 1 3 RANGE C...

Page 36: ...BASE 11 read port D I high byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Value DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 BASE 11 write port D O high byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Value DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 D A output registers BASE 4 5 Write only registers BASE 4 and 5 accept data for D A output BASE 4 D A output low byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Value DA3 DA2 DA1 DA0 X X X X BASE 5 D A outp...

Page 37: ...he A D conversion is in progress MUX Single ended differential channel indicator 0 8 differential channels 1 16 single ended channels INT Data valid 0 No A D conversion has been completed since the last time the INT bit was cleared Values in the A D data registers are not valid data 1 The A D conversion has finished and converted data is ready If the INTE bit of the control register BASE 9 is set ...

Page 38: ...ter BASE 9 provides information on the PCL 818L s operating modes BASE 9 Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Value INTE I2 I1 I0 X DMAE ST1 ST0 INTE Disable enable PCL 818L generated interrupts 0 Disables interrupt generation No interrupt signal can be sent to the PC bus 1 Enables interrupt generation If DMAE 0 the PCL 818L will generate an interrupt when it completes an A D conversion Use this se...

Page 39: ...d by another I O device DMAE Disable Enable PCL 818L DMA transfers 0 Disables DMA transfer 1 Enables DMA transfer Each A D conversion initiates two successive DMA request signals These signals cause the 8237 DMA controller to transfer two bytes of conversion data from the PCL 818L to memory Note You must program the PC s 8237 DMA controller and the DMA page register before you set DMAE to 1 ST1 to...

Page 40: ...cks trigger pulses sent from the pacer to the A D until TRIG0 is taken high TC1 Counter 0 input source mode 0 Sets Counter 0 to accept external clock pulses 1 Connects Counter 0 internally to a 100 KHz clock source Programmable timer counter registers BASE 12 13 14 15 The four registers located at addresses BASE 12 BASE 13 BASE 14 and BASE 15 are used for the Intel 8254 programmable timer counter ...

Page 41: ...Chapter 5 A D conversion 37 C H A P T E R 5 A D conversion ...

Page 42: ... 1 It stores the A D low byte data in bits D4 to D7 AD0 to AD3 of BASE 0 and high byte data in bits D0 to D7 AD4 to AD11 of BASE 1 The least significant bit is AD0 and the most significant bit is AD11 You can read the source channel number corresponding to the A D data form bits D0 to D3 C0 to C3 of BASE 0 A D data register format is BASE 0 read only A D low byte and channel number Bit D7 D6 D5 D4...

Page 43: ...an range The MUX scan register is a read write register at address BASE 2 Bits D0 to D3 hold the starting channel number and positions D4 to D7 hold the stop scan channel number When you set the PCL 818L for eight differential input channels bits CH3 and CL3 must be zero The MUX scan register data format is BASE 2 write start and stop scan channels Bit D7 D6 D5 D4 D3 D2 D1 D0 Value CH3 CH2 CH1 CH0...

Page 44: ...iggering rate is too slow 2 You can use the PCL 818L s on board Intel 8254 programmable interval timer counter to generate timing related signals Counters 1 and 2 of the Intel 8254 can provide A D converter trigger pulses with precise periods The 8254 can generate pacer output between 2 5 MHz and 71 minutes per pulse Chapter 8 covers the details of the Intel 8254 timer counter Pacer triggering is ...

Page 45: ...nsfer an interrupt routine handler program transfers data from the card s A D data registers to a previously defined memory segment in the PC At the end of each conversion the EOC signal generates an interrupt and the interrupt handler routine performs the transfer You must specify the interrupt control bit and the interrupt level selection bits in the PCL 818L control register BASE 9 before you u...

Page 46: ...r User s Manual for more information Do the following to perform software trigger and program controlled data transfer without the PCL 818L driver 1 Set the input range for each A D channel 2 Set the input channel by specifying the MUX scan range 3 Trigger the A D conversion by writing to the A D low byte register BASE 0 with any value 4 Check for the end of the conversion by reading the A D statu...

Page 47: ...Chapter 6 D A conversion 43 6 D A conversion C H A P T E R ...

Page 48: ...A and not released to the output After you write the high byte the low byte and high byte are added and passed to the D A converter This double buffering process protects D A data integrity through a single step update The PCL 818L provides a precision fixed internal 5 V or 10 V reference selectable by means of Jumper JP5 This reference voltage is available at connector CN3 pin 11 If you use this ...

Page 49: ...tal attenuator by inputting variable AC or DC references or as a generator of arbitrary waveforms In your application program you can perform D A functions by addressing the PCL 818L s registers directly or you can take advan tage of the Advantech driver functions For more information see the user s manual for the driver ...

Page 50: ...46 PCL 818L User s Manual ...

Page 51: ...Chapter 7 Digital input and output 47 7 Digital input and output C H A P T E R ...

Page 52: ...format for each register appears below BASE 3 read port D I low byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Value DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 BASE 3 write port D O low byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Value DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 BASE 11 read port D I high byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Value DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 BASE 11 write port D O high byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Val...

Page 53: ...Chapter 8 Programmable counter timer 49 8 Programmable timer counter C H A P T E R ...

Page 54: ...cy and the output of Counter 1 connects to the input of Counter 2 The output of Counter 2 is internally configured to provide trigger pulses to the A D converter but you can also access it for your own use from connector CN3 pin 37 Counter 0 is not used by the PCL 818L and is available for your use You can access it through CN3pin18 Counter read write and control registers The 8254 programmable in...

Page 55: ...C1 SC0 0 0 0 1 0 1 2 1 0 Read back command 1 1 RW1 RW0 Select read write operation Operation RW1 RW0 Counter latch 0 0 Read write LSB 0 1 Read write MSB 1 0 Read write LSB first 1 1 then MSB M2 M1 M0 Select operating mode M2 M1 M0 Mode 0 0 0 0 interrupt on terminal count 0 0 1 1 programmable one shot X 1 0 2 Rate generator X 1 1 3 Square wave rate generator 1 0 0 4 Software triggered strobe 1 0 1 ...

Page 56: ...ol register data format then becomes BASE 15 8254 control read back mode Bit D7 D6 D5 D4 D3 D2 D1 D0 Value 1 1 CNT STA C2 C1 C0 X CNT 0 Latch count of selected counter s STA 0 Latch status of selected counter s C2 C1 C0 Select counter for a read back operation C2 1 select Counter 2 C1 1 select Counter 1 C0 1 select Counter 0 If you set both SC1 and SC0 to 1 and STA to 0 the register selected by C2...

Page 57: ...de of operation is set After you load the count into the selected count register the output will remain low and the counter will count When the counter reaches the terminal count its output will go high and remain high until you reload it with the mode or a new count value The counter continues to decrement after it reaches the terminal count Rewriting a counter register during counting has the fo...

Page 58: ...n numbers and will go low for the other half of the count This is accomplished by decreasing the counter by two on the falling edge of each clock pulse When the counter reaches the terminal count the state of the output is changed the counter is reloaded with the full count and the whole process is repeated If the count is odd and the output is high the first clock pulse after the count is loaded ...

Page 59: ...eparate addresses and each control byte specifies the counter it applies to by SC1 SC0 no instructions on the operating sequence are required Any programming sequence following the 8254 conven tion is acceptable There are three types of counter operation read load LSB read load MSB and read load LSB followed by MSB It is important that you make your read write operations in pairs and keep track of...

Page 60: ...two ways The first way is to set bits RW1 and RW0 to 0 This latches the count of the selected counter in a 16 bit hold register The second way is to perform a latch operation under the read back command Set bits SC1 and SC0 to 1 and CNT 0 The second method has the advantage of operating several counters at the same time A subsequent read operation on the selected counter will retrieve the latched ...

Page 61: ...Chapter 9 Direct memory access operation 57 9 Direct memory access operation C H A P T E R ...

Page 62: ...ons Channel 3 is normally used for hard disk operations Channel 1 is not reserved for any internal operations and is available for your applications Each channel has two associated control signals associated with it The DMA request signal DRQ triggers a DMA operation and the DMA acknowledge signal DACK authorizes the 8237 to start the data transfer The 8237 DMA chip has four operating modes single...

Page 63: ...L 818L jumper JP1 accordingly 2 If you will be using the PCL 818L driver for your DMA transfer programming see the Software Drivers User s Manual for information 3 If you choose to conduct your own DMA operation you will need to have a solid understanding of the PC 8237 DMA controller and the PCL 818L Make sure you perform the following steps in your DMA transfer a Initialize 8237 DMA controller r...

Page 64: ...60 PCL 818L User s Manual ...

Page 65: ......

Page 66: ...Appendix B Connector Switch and VR Locations 63 B Connector switch and VR Locations A P P E N D I X ...

Page 67: ...nter output SW1 Base address JP1 DMA level 1 or 3 JP2 10 MHz 1 MHz time base JP3 TRIG0 GATE0 connection JP4 D A reference selection internal external JP5 5 V 10 V internal reference JP6 Differential or single ended inputs JP7 A D input voltage range selection 5 or 10 JP8 to JP11 Digital output connector CN1 or CN3 daughterboard ctrl VR1 A D full scale VR2 A D bipolar offset VR3 D A full scale VR4 ...

Page 68: ...Appendix C PC I O port address map 65 C PC I O port address map A P P E N D I X ...

Page 69: ...eserved 201 Game control 202 277 Reserved 278 27F LPT2 2nd printer port 280 2F7 Reserved 2F8 2FF COM2 300 377 Reserved 378 37F LPT1 1st printer port 380 3AF Reserved 3B0 3BF Mono Display Print adapter 3C0 3CF Reserved 3D0 3DF Color Graphics 3E0 3EF Reserved 3F0 3F7 Floppy disk drive 3F8 3FF COM1 ...

Page 70: ...Appendix D Calibration 67 D Calibration A P P E N D I X ...

Page 71: ...iving safe and easy access to the PCL 818L during calibra tion or other tasks The CALB EXE makes calibration easy It leads you through the calibration and setup procedure with a variety of prompts and graphic displays showing you all of the correct settings and adjustments The explanatory material in this section is brief intended for use in conjunction with the calibration program VR assignment T...

Page 72: ... equals the reference voltage minus 1 LSB but with the opposite sign For example if Vref is 5 V then Vout should be 4 9988 V If Vref is 10 V Vout should be 9 9975 V A D calibration Regular and accurate calibration procedures ensure maximum possible accuracy The CALB EXE calibration program leads you through the whole A D offset and gain adjustment procedure The basic steps are outlined below 1 Sho...

Page 73: ...70 PCL 818L User s Manual ...

Page 74: ... This is the standard setup for the PCL 818L revision A1 The default jumper setting on the PCL 818L revision A2 is with the jumpers set to the S right hand side In this configuration the digital output signals D0 to D3 will be on the 37 pin connector CN3 The signal pins on CN1 will now be floating D0 D1 D2 D3 S0 S1 S2 S3 JP8 to JP11 Digital Output to CN3 37 pin JP8 to JP11 Digital Output to CN1 20...

Page 75: ...2 PCL 818L User s Manual ...

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