PCL-818 Series User Manual
28
We recommend that you leave JP5 set to the default DIO and DI2,
because the software driver requires this setting.
FIFO Interrupt Selection (JP9)
The PCL-818HD/HG’s JP9 controls the interrupt (2 through 7) that the
FIFO generates when it is half full. The FIFO interrupt control register,
BASE+6, enables and disables this interrupt. Jumper settings are as fol-
lows:
FIFO IRQ Select (IRQ2 Default)
Digital Output, 20-pin or 37-pin Connector (JP1-4)
The PCL-818HD/L’s JPI to JP4 switch digital output channels O to 3
between the card's 20-pin connector and 37-pin connector. If you set the
jumpers to the left (D) side, the digital output signals will come out on
connector CN1 (20-pin). If you set the jumpers to the right (S) side, the
output signals will come out on connector CN3 (37-pin).
These four digital output signals select the analog input channel when
you use a multiplexer/amplifier daughter board. Daughter boards with a
DB-37 connector, such as the PCLD-789D, read the digital output signals
from the DB-37 connector (CN3). With other daughter boards you will
need to connect an external 20-pin flat cable from CN1 to the daughter
board.
Summary of Contents for PCL-818 Series
Page 1: ...PCL 818 Series 12 bit ISA Multifunction Card User Manual ...
Page 14: ...PCL 818 Series User Manual 6 Figure 1 1 Installation Flow Chart ...
Page 28: ...PCL 818 Series User Manual 20 ...
Page 45: ...2 APPENDIX A Specifications ...
Page 49: ...2 APPENDIX B Block Diagram ...
Page 51: ...2 APPENDIX C Register Structure Format ...
Page 71: ...2 APPENDIX D Calibration ...