PCL-818 Series User Manual
60
C.16 Clear FIFO Interrupt Request — BASE+14H
Write any value to this I/O port to clear the FIFO's interrupt request.
Table C-15 Register for Clear FIFO Interrupt Request
C.17 A/D Data and Channel from FIFO - BASE + 17/18H
The PCL-818HD/HG stores data from A/D conversions in a 1 K word
First-In First-Out (FIFO) data buffer. Registers at BASE+17H and
BASE+18H store the channel number and data. The register at
BASE+19H clears the FIFO buffer and sets its empty flag (EF).
Table C-16 Register for A/D Data and Channel from FIFO
AD11 ~ AD0 Analog to digital data
AD0
the least significant bit (LSB) of the A/D data
AD11
the most significant bit (MSB)
C3 ~ C0
A/D channel number from which the data is derived
C0
the least significant bit (LSB) of the channels
C3
the most significant bit (MSB)
Write
Clear FIFO Interrupt Request
Bit #
7
6
5
4
3
2
1
0
BASE + 14H
X
X
X
X
X
X
X
X
Note:
This register is not used for PCL-818L.
Read
A/D data and channels from FIFO
Bit #
7
6
5
4
3
2
1
0
BASE + 17H AD3
AD2
AD1
AD0
C3
C2
C1
C0
BASE + 18H AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
Note:
This register is not used for PCL-818L.
Summary of Contents for PCL-818 Series
Page 1: ...PCL 818 Series 12 bit ISA Multifunction Card User Manual ...
Page 14: ...PCL 818 Series User Manual 6 Figure 1 1 Installation Flow Chart ...
Page 28: ...PCL 818 Series User Manual 20 ...
Page 45: ...2 APPENDIX A Specifications ...
Page 49: ...2 APPENDIX B Block Diagram ...
Page 51: ...2 APPENDIX C Register Structure Format ...
Page 71: ...2 APPENDIX D Calibration ...
