A/D Conversion
This chapter provides a complete explanation of how to use the PCL-812PG A/D conversion func-
tions. It covers A/D data format, input range selection, MUX multiplier channel control, trigger
modes and data transfer in the first sections. The last section give step-by-step implementation
guidelines on A/D operations.
5.1 A/D Data Format and Status Register
When the PCL-812PG performs 12-bit A/D conversions, an 8-bit register is not big enough to
accommodate all 12 bits of data. Therefore A/D data are stored in two registers located at address
BASE +4 and BASE +5. The A/D low byte data are in the positions D0 (AD0) through D7 (AD7)
of BASE +4 and high byte data are in the positions D0 (AD8) through D3 (AD11) of BASE +5.
The least significant bit is AD0 and the most significant bit is AD11. The A/D channel number
from which the conversion data derived is available at register BASE +10 postion D0 (CL0) to D3
(CL3). The gain is set at register BASE +9 position D0 (R0) to D2 (R2).
The data format of the A/D data registers is:
A/D Low byte and Channel number.
A/D High byte
5.2 MUX Setting
Data Format:
5.3 Gain Setting
Data Format:
5.4 Trigger Mode
The PCL-812PG A/D conversions can be triggered in any one of three ways - software trigger, on-
board programmable pacer or external pulse trigger.
The software trigger is controlled by the application program issued software command. Writing to
register BASE +12 with any value causes a software trigger. This trigger mode is normally not used
in high-speed A/D applications due to the limitations of the applications program execution time.
The PCL-812PG uses the Intel 8253 programmable interval timer/counter. Counters 1 and 2 of the
Intel 8253 are configured to be a pacer to offer A/D converter trigger pulses with precise periods in
the pacer trigger mode. The pacer output of the PCL-812PG is between 0.5 MHz and 35 minutes/
pulse. Chapter 8 covers the details of using the Intel 8253 timer/counter. The pacer trigger mode is
ideal for interrupt and DMA data transfer which normally are used in A/D applications requiring a
higher conversion speed.
The PCL-812PG direct external trigger pulses are controlled through EXT.TRG (connector CN5 pin
1). This type of trigger mode is mostly used in A/D applidcations requiring A/D conversions not
periodically but conditionally, e.g. thermocouple temperature control.
5.5 A/D Data Transfer
There are three possbile ways to perform the PCL-812PG A/D data transfer - program control,
interrupt routine or DMA.
The program control data transfer uses the polling concept. After the A/D converter has been
triggered, the application program checks the data ready (DRDY) bit of the A/D high byte register.
If the DRDY bit is 0, the converted data is moved from the A/D data register to computer memory
by application program control.
In interrupt routine transfer, data is transferred from the A/D data registers to a previously defined
memory segment by the interrupt routine handler. At the end of each conversion, the data ready
signal generates an interrupt which enables the interrrupt handler routine to perform the transfer.
The interrrupt level selection on JP5, interrupt vector, interrupt controller 8259 and interrupt control
bit in the PCL-812PG control register (BASE +11) must be specified before the use of an interrupt
