2 0
2 0
2 0
2 0
2 0
PCL-812PG User's Manual
DMA 1:
DMA 3:
2.2.4 Trigger Source Selection
Jumper Name: JP1
The A/D conversion trigger source can be internal on-board
programmable pacer or external pulse signal (connector CN5 pin
1)
Internal pacer trigger:
2.2.5 User's Counter Input Clock Selection (JP2)
The programmable timer/counter has 3 channel 16 bit counters.
Channel 1 and channel 2 are configured as internal pacer and
channel 0 is left for user's applications. The clock input of
channel 0 can be internal 2 MHz clock or external clock signal
from connector CN5 pin 8.
Internal 2 MHz clock:
External clock:
2.2.6 IRQ Level Selection (JP5)
The interrupt caused by A/D conversion completion can be level
2 to 7, 10, 11, 12, 14, 15. It is selected by JP5. The user must be
aware there is no other add-on card sharing the same interrupt
level.
No interrupt:
IRQ level 2:
2.2.7 D/A Reference Source Selection (JP3, JP4)
The reference voltage of D/A converters can be the internally
generated -5 or -10 V or an external reference voltage from
connector CN2 pin 17 or pin 19. The reference source of D/A
channel 1 (2) is selected by JP3 (4).
