Advantech PCI-1243U, User Manual, Page: 51 / 94

43 Chapter 4
Command Buffers: WR0, WR4, WR8 and WR12
Each of the three channels has a command buffer which enables individ-
ual programming. Channel l's command buffer is BASE + 0, Channel 2's
is BASE + 4, Channel 3's is BASE + 8 and Channel 4's is BASE + 12. A
command can be written to any of the three buffers, and the appropriate
channel will respond to the command.
Low Data Buffers: WR1, WR5, WR9 and WR13
Low data-buffer for each channel is found at BASE + 1, BASE + 5,
BASE + 9 and BASE + 13, for channel 1, channel 2, channel 3 and chan-
nel 4 respectively. During writing (output), these buffers contain data bits
0-7 of the respective channels.
Middle Data Buffers: WR2, WR6, WR10 and WR14
Middle data-buffer for each channel is found at BASE +2, BASE +6,
BASE +10 and BASE +14, for channel 1, channel 2, channel 3 and chan-
nel 4 respectively. When writing (output), these buffers contain data bits
8-15 of the respective channels.
High Data Buffers: WR3, WR4, WR11 and WR15
High data-buffer for each channel is found at BASE +3, BASE +7, BASE
+11 and BASE +15, for channel 1, channel 2, channel 3 and channel 4
respectively. When writing (output), these buffers contain data bits 16 -23
of the respective channels.