Advantech PCI-1220U, User Manual, Page: 38 / 56

PCI-1220U User Manual 32
3.15 I/O Signal Timing
3.15.1 Power On RESET
Figure 3.21: Timing Diagram of Power On Reset
• Output pulses (nP ± P, nP ± N) for drive control and general purpose
output signals (nOUT0 ~ 3) for I/O control will be determined after 250
nsec from power on reset.
• User can access PCI-1220U only after 500 nsec from power-on reset.
3.15.2 Individual Axis Driving
Figure 3.22: Individual Axis Driving
• The maximum time to output command pulse after first pulse command
is about 650nsec.
• When pulse/direction mode, the direction signal will valid after 275
nsec and pulse output will vaild after 375 nsec after direction signal.