Advantech ITA-3650G Series, User Manual

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ITA-3650G_Series User Manual 50
The ITA-3650G’s watchdog timer can be used to monitor the software operations and
take corrective action if the software fails to function within the programmed period.
This chapter describes the operation of the watchdog timer and procedures for pro-
gramming it.
A.1 Watchdog Timer Overview
The watchdog timer is built into the super I/O controller NCT6116D and provides the
following user-programmable functions:
 Can be enabled/disabled via software
 Timer can be set from 1 to 255 seconds or 1 to 255 minutes
 Generates an interrupt or reset signal if the software fails to reset the timer
before timeout
A.2 Programming the Watchdog Timer
The I/O port address of the watchdog timer is A00h (hex).
Table A.1: Watchdog Timer Registers
Address: A00h (hex)
Register Shift Read/Write Description
65 (hex) write Set seconds or minutes as units for the timer.
Write 0 to bit 7: Set seconds as the counting unit
[default].
Write 1 to bit 7: Set minutes as the counting unit.
66 (hex) write 0: Stop timer [default].
01~FF (hex): The amount of the count, in seconds
or minutes, depends on the value set in register 65
(hex). This number decides how long the watchdog
timer waits for strobe before generating an inter-
rupt or reset signal. Writing a new value to this reg-
ister can reset the timer to count with the new
value.
67 (hex) read/write Configure the watchdog timer
Bit 1:Write 1 to enable the keyboard to reset the
timer, 0 to disable [default]
Bit 2: Write 1 to enable mouse to reset the timer, 0
to disable [default].
Bit 7~4: Set the interrupt mapping of the watchdog
timer:
1111=IRQ15
……
0011=IRQ3
0010=IRQ2
0001=IRQ1
0000=Disable [default]
68 (hex) read/write Control the watchdog timer
Bit 0: Read the watchdog state; 1= Timer timeout
Bit 2: Write 1 to immediately generate timeout sig-
nal, and automatically return to 0 (write only).
Bit 3: Write 1 to allow triggering of the timer timeout
when P20 is effective, 0 to disable [default].