ADLINK Technology PXIe-3988, User Manual

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BIOS Setup 57
PXIe-3988
B.6.2 PCH-IO Configuration
B.6.2.1 PCI Express Configuration
PEG 0:6:0 Info only Link lanes and mode
Enable root port
Auto
Disable
Enable
Auto/Enable/Disable the PCI
Express bus root port
Max Link speed
Auto
Gen1
Gen2
Gen3
Sets maximum PCI Express link
capability of the PCI Express
bus root port
Feature Options Description
PCI Express Clock
Gating
Enabled
Disabled
Enable/Disable PCI Express
Clock Gating
DMI Link ASPM control
Enabled
Disabled
Enable/Disable Native Active
State Power Management
PCIE port assigned to
LAN
Info only
PCIe port number assigned to
LAN
Compliance Test Mode
Enabled
Disabled
Enable when using Compliance
Load Board.
PCIe-USB Glitch W/A
Enabled
Disabled
PCIe-USB Glitch W/A for bad
USB device(s) connected
behind PCIE/PEG Port.
PCIE function swap
Enabled
Disabled
When Disabled, prevents PCIE
root port function swap. If any
function other than 0th is
enabled, 0th will become
visible.
PCIE Ports 0-3
Configuration
Info only
PCI Express port configuration
info
Feature Options Description