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ADLINK Technology NuDAQ, User Manual

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22

Hardware Information

Pin Definition

Pin

Definition

IDO_n

Isolated digital output channel n

VDD9

common VDD junction for input channel 64-71

VDD10

common VDD junction for input channel 72-79

VDD11

common VDD junction for input channel 80-87

VDD12

common VDD junction for input channel 88-95

VDD13

common VDD junction for input channel 96-103

VDD14

common VDD junction for input channel 104-111

VDD15

common VDD junction for input channel 112-119

VDD16

common VDD junction for input channel 120-127

IGND

Ground return path for isolated output channels

V5V

Onboard un-regulated 5V power supply output

N/C

No Connect

Summary of Contents for NuDAQ

Page 1: ...Advance Technologies Automate the World Manual Rev 2 50 Revision Date May 7 2013 Part No 50 11218 2010 NuDAQ PCI 7442 7443 7444 128 CH 64 CH Isolated Digital I O Cards User s Manual ...

Page 2: ...ven if advised of the possibility of such damages This document contains proprietary information protected by copy right All rights are reserved No part of this manual may be repro duced by any mechanical electronic or other means in any form without prior written permission of the manufacturer Trademarks NuDAQ NuIPC DAQBench are registered trademarks of ADLINK TECHNOLOGY INC Product names mention...

Page 3: ...2099 Mailing Address 8900 Research Drive Irvine CA 92618 USA ADLINK TECHNOLOGY EUROPEAN SALES OFFICE Sales Service emea adlinktech com Toll Free 49 211 4955552 Fax No 49 211 4955557 Mailing Address Nord Carree 3 40477 Düsseldorf Germany ADLINK TECHNOLOGY SINGAPORE PTE LTD Sales Service singapore adlinktech com Telephone No 65 6844 2261 Fax No 65 6844 2263 Mailing Address 84 Genting Lane 07 02A Cit...

Page 4: ...dongli Plaza No 1 Shangdidonglu Haidian District Beijing China ADLINK TECHNOLOGY SHANGHAI Sales Service market adlinkchina com cn Telephone No 86 21 6495 5210 Fax No 86 21 5450 0414 Mailing Address Floor 4 Bldg 39 Caoheting Science and Technology Park No 333 Qinjiang Road Shanghai China ADLINK TECHNOLOGY SHENZHEN Sales Service market adlinkchina com cn Telephone No 86 755 2643 4858 Fax No 86 755 2...

Page 5: ...Chapter 1 Introduction This chapter intoduces the NuDAQ digital input output PCI cards including the card features spec ifications software support information and package contents Chapter 2 Hardware Information This chapter presents the cards layout and pin definitions for internal and external con nectors Chapter 3 Operation Theory This section illustrates the tech nology features and functions ...

Page 6: ...instructions properly NOTE Additional information aids and tips that help you per form particular tasks IMPORTANTCritical information and instructions that you MUST perform to complete a task WARNING Information that prevents physical injury data loss mod ule damage program corruption etc when trying to com plete a particular task ...

Page 7: ...7442 Pin Assignments 13 CN2 Connector 13 CN1 Connector 15 2 3 PCI 7443 Pin Assignments 17 CN2 Connector 17 CN1 Connector 19 2 4 PCI 7444 Pin Assignments 21 CN2 Connector 21 CN1 Connector 23 2 5 TTL I O Connector Pin Assignments 25 JP3 25 JP4 25 2 6 Board ID S1 26 3 Operation theory 27 3 1 Isolated digital input 27 3 2 Change of State COS interrupt 28 Overview 28 COS detection 28 COS detection arch...

Page 8: ...INT Control Hot Reset and Hold Control Register 45 4 2 PCI 7443 I O Registers 47 Isolated Digital Input Registers 47 COS Interrupt Control Registers 48 Interrupt Status COS INT Control Read Back Registers 51 COS Setup Latch Registers 53 TTL IO Setup Status DO and DI Register 55 4 3 PCI 7444 I O Registers 57 Isolated Digital Output Read Back Registers 57 Power up DO Setup Read Back Register 59 WDT ...

Page 9: ...List of Tables iii List of Tables Table 2 1 TTL IO JP3 Connector Pin Assignments 25 Table 2 2 TTL IO JP4 Connector Pin Assignments 25 Table 2 3 Board ID Settings 26 ...

Page 10: ...iv List of Tables ...

Page 11: ...t 10 Figure 2 3 PCI 7444 Layout 11 Figure 2 4 PCI 7440 Series Card Bracket 12 Figure 2 5 PCI 7440 Series Connector Pin Reference 12 Figure 3 1 Photo Coupler 27 Figure 3 2 COS Timing 28 Figure 3 3 COS Detection Architecture 29 Figure 3 4 Common Ground Connection of Isolated Digital Output 30 ...

Page 12: ...v List of Figures ...

Page 13: ...d industrial applica tions X PCI 7442 Isolated 64 CH DI and 64 CH DO card X PCI 7443 Isolated 128 CH DI card X PCI 7444 Isolated 128 CH DO card The card series provide a robust 1 250 VRMS isolation protection which is suitable for most industrial applications For PCI chassis with multiple PCI 7442 7443 7444 installed the board ID design feature enables convenient identification of the cards throug...

Page 14: ... PnP Yes Yes Yes Isolated digital input channels 64 128 Isolated digital output channels 64 128 Change of state COS detection 64 128 Channels with 28 V voltage protection 64 128 Channels with 250 mA sink current 64 128 Channels with digital output status read back 64 128 DO value retained after hot system reset Yes Yes Programmable power up DO status Yes Yes Programmable safety DO status function ...

Page 15: ...S Optical isolated digital output PCI 7442 PCI 7444 only Output channels 64 PCI 7442 128 PCI 7444 Output type Open drain power MOSFET driver Output device TPC8206 Output range 5 V 40 V Sink current 250 mA for all channel 60 C 100 duty 300 mA max Isolation voltage 1250 VRMS Data transfer Programmed I O Isolated 5V power supply PCI 7442 PCI 7444 only Output voltage 5 V Output current 100 mA maximum ...

Page 16: ...on even during WDT interruption Digital output value retention after hot system reset General specifications Dimensions 174 7 mm L x 106 7 mm W standard PCI Bus 32 bit PCI bus Operating temperature 0 C 60 C Storage temperature 40 C 80 C Humidity 5 to 85 non condensing Power Power consumption PCI 7442 5 V at 800 mA typical PCI 7443 5 V at 550 mA typical PCI 7444 5 V at 800 mA typical ...

Page 17: ...e package X PCI 7442 PCI 7443 PCI 7444 card X ADLINK All in One CD X User s manual If any of the items is damaged or missing contact your dealer immediately NOTE The packaging of OEM versions with non standard con figuration functionality or package may vary according to different configuration requests CAUTION The boards must be protected from static discharge and physical shock Never remove any ...

Page 18: ... across Windows 98 NT 2000 XP That means all applications developed with PCIS DASK are compatible across Windows 98 NT 2000 XP The devel oping environment can be VB VC Delphi BC5 or any Win dows programming language that allows calls to a DLL The user s guide and function reference manual of PCIS DASK are in the CD Refer to the manual files in the All in One CD Manual_PDF Software PCIS DASK These ...

Page 19: ...s familiar with ActiveX controls and VB VC programming to use the DAQBench ActiveX Con trol component library for developing applications The DAQBench is designed under Windows NT 98 environment For more information about DAQBench refer to the user s guide in the All in One CD ...

Page 20: ...8 Introduction ...

Page 21: ...in assignments 2 1 Card Layout Figure 2 1 shows the location of the PCI 7442 connectors switch and jumpers Figure 2 1 PCI 7442 Layout 1 CN2 64 CH isolated digital output connector 2 CN1 64 CH isolated digital input connector 3 S1 Board ID DIP switch 4 JP3 16 CH TTL0 15 TTL I O connector 5 JP4 16 CH TTL15 31 TTL I O connector 2 3 4 5 1 ...

Page 22: ...onnectors and DIP switch Figure 2 2 PCI 7443 Layout 1 CN2 64 CH isolated digital input connector IDI 64 127 2 CN1 64 CH isolated digital input connector IDI 0 63 3 S1 Board ID DIP switch 4 JP3 16 CH TTL0 16 TTL I O connector 5 JP4 16 CH TTL16 31 TTL I O connector 2 3 4 5 1 ...

Page 23: ...nnectors and DIP switch Figure 2 3 PCI 7444 Layout 1 CN2 64 CH isolated digital output connector IDO 64 127 2 CN1 64 CH isolated digital output connector IDO 0 63 3 S1 Board ID DIP switch 4 JP3 16 CH TTL0 15 TTL I O connector 5 JP4 16 CH TTL15 31 TTL I O connector 2 3 4 5 1 ...

Page 24: ...ence Figure 2 5 PCI 7440 Series Connector Pin Reference CN2B CN1B CN2A CN1A Terminal B68 Terminal B34 Terminal A1 Terminal A35 CN2B CN2A Terminal A68 Terminal B35 Terminal B1 Terminal A34 Terminal B68 Terminal B34 Terminal B1 Terminal B35 Terminal A68 Terminal A34 Terminal A35 Terminal A1 CN1B CN1A ...

Page 25: ...GND A14 A48 IGND IDO_58 B54 B20 IDO_50 IGND A15 A49 IGND IDO_57 B53 B19 IDO_49 IGND A16 A50 IGND IDO_56 B52 B18 IDO_48 N C A17 A51 N C N C B51 B17 N C IDO_16 A18 A52 IDO_24 IGND B50 B16 IGND IDO_17 A19 A53 IDO_25 IGND B49 B15 IGND IDO_18 A20 A54 IDO_26 IGND B48 B14 IGND IDO_19 A21 A55 IDO_27 IGND B47 B13 IGND IDO_20 A22 A56 IDO_28 IGND B46 B12 IGND IDO_21 A23 A57 IDO_29 IGND B45 B11 IGND IDO_22 A2...

Page 26: ...on VDD junction for input channel 16 23 VDD4 common VDD junction for input channel 24 31 VDD5 common VDD junction for input channel 32 39 VDD6 common VDD junction for input channel 40 47 VDD7 common VDD junction for input channel 48 55 VDD8 common VDD junction for input channel 56 63 IGND Ground return path for isolated output channels V5V Onboard un regulated 5V power supply output N C No Connect...

Page 27: ...2 IDI_58 B54 B20 IDI_50 COM1 A15 A49 COM2 IDI_57 B53 B19 IDI_49 COM1 A16 A50 COM2 IDI_56 B52 B18 IDI_48 N C A17 A51 N C N C B51 B17 N C IDI_16 A18 A52 IDI_24 COM6 B50 B16 COM5 IDI_17 A19 A53 IDI_25 COM6 B49 B15 COM5 IDI_18 A20 A54 IDI_26 COM6 B48 B14 COM5 IDI_19 A21 A55 IDI_27 COM6 B47 B13 COM5 IDI_20 A22 A56 IDI_28 COM6 B46 B12 COM5 IDI_21 A23 A57 IDI_29 COM6 B45 B11 COM5 IDI_22 A24 A58 IDI_30 CO...

Page 28: ... 0 7 COM2 common junction for input channel 8 15 COM3 common junction for input channel 16 23 COM4 common junction for input channel 24 31 COM5 common junction for input channel 32 39 COM6 common junction for input channel 40 47 COM7 common junction for input channel 48 55 COM8 common junction for input channel 56 63 N C No Connect ...

Page 29: ...4 A48 COM10 IDI_122 B54 B20 IDI_114 COM9 A15 A49 COM10 IDI_121 B53 B19 IDI_113 COM9 A16 A50 COM10 IDI_120 B52 B18 IDI_112 N C A17 A51 N C N C B51 B17 N C IDI_80 A18 A52 IDI_88 COM14 B50 B16 COM13 IDI_81 A19 A53 IDI_89 COM14 B49 B15 COM13 IDI_82 A20 A54 IDI_90 COM14 B48 B14 COM13 IDI_83 A21 A55 IDI_91 COM14 B47 B13 COM13 IDI_84 A22 A56 IDI_92 COM14 B46 B12 COM13 IDI_85 A23 A57 IDI_93 COM14 B45 B11 ...

Page 30: ...M10 common junction for input channel 72 79 COM11 common junction for input channel 80 87 COM12 common junction for input channel 88 95 COM13 common junction for input channel 96 103 COM14 common junction for input channel 104 111 COM15 common junction for input channel 112 119 COM16 common junction for input channel 120 127 N C No Connect ...

Page 31: ...2 IDI_58 B54 B20 IDI_50 COM1 A15 A49 COM2 IDI_57 B53 B19 IDI_49 COM1 A16 A50 COM2 IDI_56 B52 B18 IDI_48 N C A17 A51 N C N C B51 B17 N C IDI_16 A18 A52 IDI_24 COM6 B50 B16 COM5 IDI_17 A19 A53 IDI_25 COM6 B49 B15 COM5 IDI_18 A20 A54 IDI_26 COM6 B48 B14 COM5 IDI_19 A21 A55 IDI_27 COM6 B47 B13 COM5 IDI_20 A22 A56 IDI_28 COM6 B46 B12 COM5 IDI_21 A23 A57 IDI_29 COM6 B45 B11 COM5 IDI_22 A24 A58 IDI_30 CO...

Page 32: ... 0 7 COM2 common junction for input channel 8 15 COM3 common junction for input channel 16 23 COM4 common junction for input channel 24 31 COM5 common junction for input channel 32 39 COM6 common junction for input channel 40 47 COM7 common junction for input channel 48 55 COM8 common junction for input channel 56 63 N C No Connect ...

Page 33: ...GND A14 A48 IGND IDO_122 B54 B20 IDO_114 IGND A15 A49 IGND IDO_121 B53 B19 IDO_113 IGND A16 A50 IGND IDO_120 B52 B18 IDO_112 N C A17 A51 N C N C B51 B17 N C IDO_80 A18 A52 IDO_88 IGND B50 B16 IGND IDO_81 A19 A53 IDO_89 IGND B49 B15 IGND IDO_82 A20 A54 IDO_90 IGND B48 B14 IGND IDO_83 A21 A55 IDO_91 IGND B47 B13 IGND IDO_84 A22 A56 IDO_92 IGND B46 B12 IGND IDO_85 A23 A57 IDO_93 IGND B45 B11 IGND IDO...

Page 34: ...DD junction for input channel 80 87 VDD12 common VDD junction for input channel 88 95 VDD13 common VDD junction for input channel 96 103 VDD14 common VDD junction for input channel 104 111 VDD15 common VDD junction for input channel 112 119 VDD16 common VDD junction for input channel 120 127 IGND Ground return path for isolated output channels V5V Onboard un regulated 5V power supply output N C No...

Page 35: ...D IDO_58 B54 B20 IDO_50 IGND A15 A49 IGND IDO_57 B53 B19 IDO_49 IGND A16 A50 IGND IDO_56 B52 B18 IDO_48 N C A17 A51 N C N C B51 B17 N C IDO_16 A18 A52 IDO_24 IGND B50 B16 IGND IDO_17 A19 A53 IDO_25 IGND B49 B15 IGND IDO_18 A20 A54 IDO_26 IGND B48 B14 IGND IDO_19 A21 A55 IDO_27 IGND B47 B13 IGND IDO_20 A22 A56 IDO_28 IGND B46 B12 IGND IDO_21 A23 A57 IDO_29 IGND B45 B11 IGND IDO_22 A24 A58 IDO_30 IG...

Page 36: ...t channel 8 15 VDD3 common VDD junction for input channel 16 23 VDD4 common VDD junction for input channel 24 31 VDD5 common VDD junction for input channel 32 39 VDD6 common VDD junction for input channel 40 47 VDD7 common VDD junction for input channel 48 55 VDD8 common VDD junction for input channel 56 63 IGND Ground return path for isolated output channels N C No Connect ...

Page 37: ...ND 10 SGND 11 TTLIO_4 12 TTLIO_12 13 TTLIO_5 14 TTLIO_13 15 TTLIO_6 16 TTLIO_14 17 TTLIO_7 18 TTLIO_15 19 SGND 20 SGND Table 2 1 TTL IO JP3 Connector Pin Assignments Pin Function Pin Function 1 TTLIO_16 2 TTLIO_24 3 TTLIO_17 4 TTLIO_25 5 TTLIO_18 6 TTLIO_26 7 TTLIO_19 8 TTLIO_27 9 SGND 10 SGND 11 TTLIO_20 12 TTLIO_28 13 TTLIO_21 14 TTLIO_29 15 TTLIO_22 16 TTLIO_30 17 TTLIO_23 18 TTLIO_31 19 SGND 2...

Page 38: ... a designated card and access it correctly through simple software programming The table below shows all the switch settings 1 means DIP is at ON position 0 means that the DIP is OFF Table 2 3 Board ID Settings Note 1 ON 0 OFF Default setting is 1111 or Board ID 0 Board ID Switch No 1 2 3 4 0 1 1 1 1 1 0 1 1 1 2 1 0 1 1 3 0 0 1 1 4 1 1 0 1 5 0 1 0 1 6 1 0 0 1 7 0 0 0 1 8 1 1 1 0 9 0 1 1 0 10 1 0 1...

Page 39: ...put channels The circuit diagram of the isolated input channel is shown in Figure 3 1 Figure 3 1 Photo Coupler The digital input is routed first through a photo coupler PC3H4 so that the connection are not polarly sensitive whether using positive or negative voltage The normal input voltage range for high state is from 5 V to 28 V ...

Page 40: ...upt request to PCI con troller COS detection Figure 3 2 is an example of an 8 CH COS operation All of the enabled DI channels signal level change will be detected to gen erate the interrupt request While the interrupt request generates the corresponding DI data will also be latched into the COS latch register In our COS archi tecture the DI data are sampled by a 33 MHz clock It means the pulse wid...

Page 41: ...s bank 0 from DI0 to DI31 and bank 1 from DI32 to 63 while PCI 7443 has four banks bank 0 from DI0 to DI31 and bank 1 from DI32 to 63 bank 2 from DI64 to DI95 and bank 3 from DI96 to 127 These banks are cascaded together toward the same IRQ line via CPLD You can use commands to know which bank or which DI line has COS when it happens Also you can use commands to disable or enable the COS function ...

Page 42: ...t the MOSFETs are protected from any high reverse voltage which can be generated by the inductance load when the output is switched from ON to OFF In addition you can read back the 64 128 CH IDO statuses to check if the sta tuses meet your purpose Figure 3 4 Common Ground Connection of Isolated Digital Output The PCI 7442 PCI 7444 provides three special functions for safety measures First the PCI ...

Page 43: ... must periodically reload the timer value by software command If the timer is not being reloaded within the specified interval the WDT module generates an overflow interruption signal When you enable the SafetyOut_Enable bit the PCI 7442 PCI 7444 would automati cally configure the 64 CH 128 CH DO safety statuses This WDT function is disabled by default 3 5 Programmable TTL Input Output The PCI 744...

Page 44: ...32 Operation theory ...

Page 45: ...ions The isolated digital input output control is by accessing registers mentioned in this chapter 4 1 PCI 7442 I O Registers Isolated Digital Input Register There are 64 isolated inputs on a PCI 7442 card The statuses of the 64 lines can be read from the four isolated input registers Each bit corresponds to each channel The bit value 1 means that the input is ON and 0 means that the input is OFF ...

Page 46: ...upt that came before the previous interrupt and has not cleared will be ignored To clear the interrupt request write 1 to the correspond ing bit CLRn The WDT INT control registers are shown below The COS interrupt is enabled by two registers Because the 64 digital inputs are divided into two 32 bit onboard buses every 32 inputs are connected to a CPLD When you enable COS interrupt EA0 BASE 0x06h t...

Page 47: ...0h Read Write W CLR1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EA1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 9 Not used Bit7 1 Not used Bit0 CLR1 COS 1 interrupt clear 1 Clear 0 No effect Bit8 EA1 COS 1 interrupt enable disable 1 Enabled 0 Disabled ...

Page 48: ...2 Bit11 Bit10 Bit9 Bit8 Bit14 12 Not used Bit0 CIS0 COS 0 interrupt status 1 COS interrupt assert 0 COS interrupt no assert Bit1 CIS1 COS 1 interrupt status 1 COS interrupt assert 0 COS interrupt no assert Bit15 COS0E COS 0 interrupt enable status 1 COS 0 interrupt enabled 0 COS 0 interrupt disabled Address BASE 0x46h Reset Value 0x0000h Read Write R Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 COS1E B...

Page 49: ...ears Since you can simply read these registers to know the statuses after interrupts these registers free the CPU from the overwhelming task of constantly polling all inputs enabling it to handle other tasks Address R W Value Mapping MSB LSB BASE 0x08h W IDI_COS_EN 15 0 BASE 0x0Ah W IDI_COS_EN 31 16 BASE 0x48h W IDI_COS_EN 47 32 BASE 0x4Ah W IDI_COS_EN 63 48 IDI_COS_EN n Change of State function e...

Page 50: ...ack Regis ter in each back You can read back the I O direction statuses to check if the settings are correct When the I O direction setting is output you can send out data through the TTL I O output channel Address R W Value Mapping MSB LSB BASE 0x0Ch W TTL_IO_SETUP 15 0 BASE 0x4Ch W TTL_IO_SETUP 31 16 Bit value 0 I O direction is input default 1 I O direction is output Address R W Value Mapping M...

Page 51: ... I O direction setting is input you can read data through the TTL I O input channel Address R W Value Mapping MSB LSB BASE 0x0Eh R TTL_IO_DI 15 0 BASE 0x4Eh R TTL_IO_DI 31 16 Bit value 0 Input is low 1 Input is high Initial value ...

Page 52: ...a will then be sent out at the same time The output device type is Open Drain Power MOSFET driver DO Send Out Start does not need any register value You only need to send out the address BASE 0x88h in Write mode after setting up all 64 bit channel output data When the back2 receives the Start command the 64 bit DO data is sent out at the same time You can check if the DO send procedure is finished...

Page 53: ...y need to send out the address BASE 0x80h in Read mode before reading back all 64 bit channel output data When the back2 receives the Start command the 64 bit DO data readback procedure proceeds You can check if the DO readback procedure is finished by get nDO_RBReady flag status Address R W Value Mapping MSB LSB BASE 0x80h R DO Read Back Start BASE 0x82h R IDO 15 0 BASE 0x84h R IDO 31 16 BASE 0x8...

Page 54: ... You may check if the procedure is finish or not by nAction_Ready flag You can read the configured power up initial DO values stored in the flash memory by sending out the Read Start command BASE 0x8Ch The read procedure starts in 50 ms When the Read Back procedure is ready nAction_Ready flag you can read back the 64 bit Power up DO Read Back Register in turn Address R W Value Mapping MSB LSB BASE...

Page 55: ...onfigure the default 64 CH safety DO values which are stored in the flash memory When WDT interrupt asserts and the SafetyOut_Enable bit is enabled the PCI 7442 enters the safety DO procedure which sends out the default safety value to 64 CH digital outputs You can program the 64 CH safety default DO values by access ing the last WDTSafety DO Setup register in turn After accessing the last WDTSafe...

Page 56: ...rts in 50 ms The finished flag can be checked by nAction_Ready flag After the Read Back procedure you can read back the 64 bit WDTSafety DO Read Back registers in turn Address R W Value Mapping MSB LSB BASE 0x96h R Read Back Start BASE 0x98h R IDO 15 0 BASE 0x9Ah R IDO 31 16 BASE 0x9Ch R IDO 47 32 BASE 0x9Ch R IDO 63 56 Bit value 0 Output Power MOSFET is OFF Initial value 1 Output Power MOSFET is ...

Page 57: ... When the system goes to an unexpected or normal hot system reset without turning off the sys tem power you can choose whether to allow the PCI 7442 board to retain the original DO values before the system hot reset or allow the PCI 7442 board to enter the power up initial procedure to send out the default initial DO values which you configured Refer to Section 3 3 for details By setting the HRHE ...

Page 58: ...it8 Bit15 7 Not used Bit0 HRHES Hot Reset Hold Enable Status 1 Enabled 0 Disabled Bit1 WDTES WDT Interrupt Enable Status 1 Enabled 0 Disabled Bit2 WIS WDT interrupt status 1 WDT interrupt does not assert 0 WDT interrupt asserts Bit3 SOES Safety Out Enable Status 1 Enabled 0 Disabled Bit4 RBRDYS DO Read Back Data Ready Status 1 Not ready 0 Ready Bit5 SRDYS DO Data Sending Finished Status 1 Not fini...

Page 59: ...ines can be read from the registers listed below Each bit corresponds to each channel Address R W Value Mapping MSB LSB BASE 0x02h R IDI 15 0 BASE 0x04h R IDI 31 16 BASE 0x42h R IDI 47 32 BASE 0x44h R IDI 63 48 BASE 0x82h R IDI 79 64 BASE 0x84h R IDI 95 80 BASE 0xC2h R IDI 111 96 BASE 0xC4h R IDI 127 112 Bit value 1 The input is ON 0 The input is OFF Inital value ...

Page 60: ... the 128 digital inputs are divided into four 32 bit onboard buses every 32 inputs are connected to a CPLD When users enable COS inter rupt EA0 BASE 0x06h the first CPLD CPLD0 produces inter rupt signal while the first 32 bit inputs IDI 31 0 have change of state When users enable COS interrupt EA1 BASE 0x46h the second CPLD CPLD1 produces interrupt signal while the second 32 bit inputs IDI 63 32 h...

Page 61: ... 9 Not used Bit7 1 Not used Bit0 CLR1 COS 1 interrupt clear 1 Clear 0 No effect Bit8 EA1 COS 0 Interrupt enable disable 1 Enabled 0 Disabled Address BASE 0x86h Reset Value 0x0000h Read Write W CLR2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EA2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 9 Not used Bit7 1 Not used Bit0 CLR2 COS 2 interrupt clear 1 Clear 0 No effect Bit8 EA2 COS 2 Interrupt en...

Page 62: ...0h Read Write W CLR3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EA3 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 9 Not used Bit7 1 Not used Bit0 CLR3 COS 3 interrupt clear 1 Clear 0 No effect Bit8 EA3 COS 3 interrupt enable disable 1 Enabled 0 Disabled ...

Page 63: ...Value 0x0000h Read Write R C3IS C2IS C1IS C0IS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 COS0E Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit14 4 Not used Bit0 CIS0 COS 0 INT Status 1 COS assert 0 COS not assert Bit1 CIS1 COS 1 INT Status 1 COS assert 0 COS not assert Bit2 CIS2 COS 2 INT Status 1 COS assert 0 COS not assert Bi3 CIS3 COS 3 INT Status 1 COS assert 0 COS not assert Bit15 COS0E COS 0...

Page 64: ...ddress BASE 0x86h Reset Value 0x0000h Read Write R Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 COS2E Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit14 0 Not used Bit15 COS2E COS 2 Interrupt enable status 1 Enabled 0 Disabled Address BASE 0xC6h Reset Value 0x0000h Read Write R Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 COS3E Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit14 0 Not used Bit15 COS3E COS ...

Page 65: ...ard generates an interrupt when the corresponding channel changes its state Address R W Value Mapping MSB LSB BASE 0x08h W IDI_COS_EN 63 0 BASE 0x0Ah W IDI_COS_EN 31 16 BASE 0x48h W IDI_COS_EN 47 32 BASE 0x4Ah W IDI_COS_EN 63 48 BASE 0x88h W IDI_COS_EN 79 64 BASE 0x8Ah W IDI_COS_EN 95 80 BASE 0xC8h W IDI_COS_EN 111 96 BASE 0xCAh W IDI_COS_EN 127 112 IDI_COS_EN n Change of State function enable of ...

Page 66: ...sters free the CPU from constantly polling all inputs and enable the system to handle more tasks Address R W Value Mapping MSB LSB BASE 0x08h R IDI_COS_LATCH_DATA 15 0 BASE 0x0Ah R IDI_COS_LATCH_DATA 31 16 BASE 0x48h R IDI_COS_LATCH_DATA 47 32 BASE 0x4Ah R IDI_COS_LATCH_DATA 63 48 BASE 0x88h R IDI_COS_LATCH_DATA 79 64 BASE 0x8Ah R IDI_COS_LATCH_DATA 95 80 BASE 0xC8h R IDI_COS_LATCH_DATA 111 96 BAS...

Page 67: ...k Regis ters You can read back the I O direction statuses to check if the settings are correct When the I O direction setting is output you can send out data through the TTL I O output channel Address R W Value Mapping MSB LSB BASE 0x0Ch W TTL_IO_SETUP 15 0 BASE 0x4Ch W TTL_IO_SETUP 31 16 Bit value 0 I O direction is input Default 1 I O direction is output Address R W Value Mapping MSB LSB BASE 0x...

Page 68: ...O direction setting is input users can read data through the TTL I O input channel Address R W Value Mapping MSB LSB BASE 0x0Eh R TTL_IO_DI 15 BASE 0x4Eh R TTL_IO_DI 31 16 Bit value 0 Input in low logic 1 Input in high logic Default ...

Page 69: ... Send Out At The Same Time Port0 Port1 All Ch does not need any register value You only need to send out the address BASE 0x08h BASE 0x12h BASE 0x14h in Write mode after setting up all 128 bit all channel or 64 bit port0 port1 channel output data When the DO back receives the Start command the 64 128 bit DO data is sent out at the same time You can check if the DO send procedure is finished by get...

Page 70: ...ceives the Start command the 64 128 bit DO data readback procedure proceeds You can check if the DO readback procedure is finished by get nDO_RBReady flag status Port0 Isolated digital output channel range from bit0 to bit63 Port1 Isolated digital output channel range from bit64 to bit127 All Ch Isolated digital output channel range from bit0 to bit127 Address R W Value Mapping MSB LSB BASE 0x00h ...

Page 71: ...ault DO values by access ing the Power up DO Setup Registers in turn After accessing the latest Power up DO Setup Register Base 0x24h the card needs at least 500 ms to finish the writing to the flash memory pro cedure You may check if the procedure is finished or not by the nAction_Ready flag Address R W Value Mapping MSB LSB BASE 0x16h W IDO 15 0 BASE 0x18h W IDO 31 16 BASE 0x1Ah W IDO 47 32 BASE...

Page 72: ...e Start command the flash reading procedure starts in 100 ms You can check if the procedure is finished by get nAction_Ready flag status Address R W Value Mapping MSB LSB BASE 0x16h R Read Back Start BASE 0x18h R IDO 15 0 BASE 0x1Ah R IDO 31 16 BASE 0x1Ch R IDO 47 32 BASE 0x1Eh R IDO 63 48 BASE 0x20h R IDO 79 64 BASE 0x22h R IDO 95 80 BASE 0x24h R IDO 111 96 BASE 0x26h R IDO 127 112 Bit value 0 Ou...

Page 73: ...erts the system process may halt or be offline This function thus prevents untoward damage You can configure the default 128 CH safety DO values which are stored in the flash memory When WDT interrupt asserts and the SafetyOut_Enable bit is enabled the PCI 7444 enters the safety DO procedure which sends out the default safety value to 128 CH digital outputs You can program the 128 CH safety defaul...

Page 74: ...g MSB LSB BASE 0x26h W IDO 15 0 BASE 0x28h W IDO 31 16 BASE 0x2Ah W IDO 47 32 BASE 0x2Ch W IDO 63 48 BASE 0x2Eh W IDO 79 64 BASE 0x30h W IDO 95 80 BASE 0x32h W IDO 111 96 BASE 0x34h W IDO 127 112 Bit value 0 Output PowerMOSFET is OFF Initial value 1 Output PowerMOSFET is ON Address R W Value Mapping MSB LSB BASE 0x28h R Read Back Start BASE 0x2Ah R IDO 15 0 BASE 0x2Ch R IDO 31 16 BASE 0x2Eh R IDO ...

Page 75: ...rforms an unexpected or abnormal hot system reset you can set the PCI 7444 to retain its original DO values before system hot reset Oth erwise the PCI 7444 enters the power up initial procedure to send out the default initial DO values you configured By setting the HRHE bit you can enable the Hot_Reset_Hold function anytime This function is applicable for unstable operating environments Address BA...

Page 76: ...inished Bit5 SRDYS DO Data Sending Finishes Status 1 Process is not finished 0 Process is finished Bit4 RBRDYS DO Read Back Data Ready Status 1 DO read back data is not ready 0 DO read back data is ready Bit3 SOES Safety Out Enable Status 1 Function is enabled 0 Function is disabled Bit2 WIS WDT Interrupt Status 1 The WDT interrupt has asserted 0 The WDT interrupt did not assert Bit1 WDTES WDT Int...

Page 77: ...d Back Regis ters You can read back the I O direction statuses to check if the directions meet your need When the I O direction setting is output you can send out data through the TTL I O output channel Address R W Value Mapping MSB LSB BASE 0x3C W TTL_IO_SETUP 15 0 BASE 0x3E W TTL_IO_SETUP 31 16 Bit value 0 I O direction is input Default 1 I O direction is output Address R W Value Mapping MSB LSB...

Page 78: ... O direction setting is input you can read data through the TTL I O input channel Address R W Value Mapping MSB LSB BASE 0x40 R TTL_IO_DI 15 0 BASE 0x42 R TTL_IO_DI 31 16 Bit value 0 Input in low logic 1 Input in high logic Default ...

Page 79: ... want to develop your own interrupt function driver both interrupt registers in PCI 9030 and in the PCI 7442 7443 7444 card have to work together For detailed information about the interrupt control register in PCI 9030 refer to the PCI 9030 databook The PCI 7442 7443 7444 card s function library provides simple and easy to use functions that handle interrupt procedures These functions eliminate t...

Page 80: ...68 Register Format ...

Page 81: ...d party products not manufactured by ADLINK will be covered by the original manufactur ers warranty X For products containing storage devices hard drives flash cards etc please back up your data before send ing them for repair ADLINK is not responsible for any loss of data X Please ensure the use of properly licensed software with our systems ADLINK does not condone the use of pirated software and...

Page 82: ...of battery fluid during or after change of batteries by customer user X Damage from improper repair by unauthorized ADLINK technicians X Products with altered and or damaged serial numbers are not entitled to our service X This warranty is not transferable or extendible X Other categories not protected under our warranty 4 Customers are responsible for shipping costs to transport damaged products ...

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