Operation Theory
39
Waveform patterns larger than 512 samples are also supported
using bus-mastering DMA transfer via the PCI controller. Data
format in FIFO is shown in Figure 4-9.
Figure 4-9: FIFO Data In/Out Structure
DMA transfers data according to channel order. Figure 4-10
shows DA channel 0 to channel 3 data, while channel 2 is
disabled.
Figure 4-10: Waveform Generation for Three Channels Update
With hardware-based waveform generation, D/A conversions
are updated automatically by the FPGA rather than by the
application software. Compare with the conventional software-
based waveform generation, the precise hardware timing
control guarantees non-distorted waveform generation even
when the host CPU is under heavy loading.
NOTE
When using waveform generation mode, both DACs
must be configured in a single mode. However, any indi-
vidual DAC can be disabled.
Waveform Generation Clock Source
When the onboard DAC receives a conversion clock signal, it
will trigger a D/A update. The update clock of PCI-9222/PCI-
9223 may come from three different clock sources: internal
hardware timer, general purpose input channel (GPI 0 ~ GPI
7), or SSI (system synchronization interface).
Summary of Contents for NuDAQ PCI-9222
Page 12: ......
Page 36: ...24 Hardware Information...
