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Operation Theory

37

In non-chaining mode, the maximum DMA data transfer size is 2M
double words (8 MB). However, by using chaining mode-scatter/
gather, there is no limitation for the DMA data transfer size. You
may also link the descriptor nodes circularly to achieve a multi-
buffered mode DMA.

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Summary of Contents for NuDAQ PCI-9222

Page 1: ...Technologies Automate the World Manual Rev 2 00 Revision Date April 24 2008 Part No 50 11237 1000 NuDAQ PCI 9222 NuDAQ PCI 9223 16 bit High Performance DAQ Card with Programmable Function I O User s...

Page 2: ...or inability to use the product or documentation even if advised of the possibility of such damages This document contains proprietary information protected by copy right All rights are reserved No pa...

Page 3: ...2099 Mailing Address 8900 Research Drive Irvine CA 92618 USA ADLINK TECHNOLOGY EUROPEAN SALES OFFICE Sales Service emea adlinktech com Toll Free 49 211 4955552 Fax No 49 211 4955557 Mailing Address No...

Page 4: ...ngli Plaza No 1 Shangdidonglu Haidian District Beijing China ADLINK TECHNOLOGY SHANGHAI Sales Service market adlinkchina com cn Telephone No 86 21 6495 5210 Fax No 86 21 5450 0414 Mailing Address Floo...

Page 5: ...ware support information and package contents Chapter 2 Hardware Information This chapter presents the card s layout connector pin assignment signal descriptions and analog input signal connection Cha...

Page 6: ...ructions properly NOTE Additional information aids and tips that help you per form particular tasks IMPORTANTCritical information and instructions that you MUST perform to complete a task WARNING Info...

Page 7: ...nment 16 CN1 CN2 Signal Descriptions 17 SSI Connector Pin Assignment 18 SSI Connector Signal Description 19 2 3 Analog Input Signal Connection 20 Types of Signal Sources 20 Input Configurations 21 3 I...

Page 8: ...TTL DI DO 47 General Purpose Timer Counter 48 Basic Timer Counter Functions 48 General Purpose Timer Counter Modes 49 Digital Waveform Acquisition and Generation 55 4 5 Isolation Encoder 57 4 6 Trigge...

Page 9: ...Table 2 5 SSI Connector Pin Assignment 18 Table 2 6 SSI Connector Signal Description 19 Table 4 1 Bipolar Analog Input Range and Output Digital Code 29 Table 4 2 Bipolar Analog Input Range and Output...

Page 10: ...er 33 Figure 4 6 Post Trigger with Retrigger 34 Figure 4 7 Gated Trigger with Finite Scan Acquisition 35 Figure 4 8 Scatter gather DMA for Data Transfer 36 Figure 4 9 FIFO Data In Out Structure 39 Fig...

Page 11: ...on 55 Figure 4 29 Digital Waveform Generation Operation 56 Figure 4 30 Encoder Isolation Input Module 57 Figure 4 31 Encoder OGRx Input 58 Figure 4 32 CW CCW Encoder Timing 58 Figure 4 33 X1 Encoder M...

Page 12: ......

Page 13: ...variety of applications including TTL digital I O high speed DIO general purpose timer counter and PWM output These cards analog input analog output and function I O are capable of functioning simult...

Page 14: ...and 16 CH TTL DO Z 2 MHz 32 CH high speed DIO Z 4 CH 32 bit 80 MHz general purpose timer counter Z 4 CH PWM outputs X 2 CH 4 MHz dedicated encoder inputs supporting AB phase and CW CCW X Four DMA cha...

Page 15: ...50 mV Operational common mode voltage range 8 V Overvoltage protection Power on Power off Continuous 30 V Continuous 30 V Continuous 30 V Continuous 30 V FIFO buffer size 1K samples Data transfers Pro...

Page 16: ...ction 23 C 5 C Number of channels 2 D A converter DAC8812 or equivalent Maximum update range 1M sample s static Resolution 16 bit FIFO size 512 samples 2 CH sharing Data transfers Programmed I O DMA O...

Page 17: ...gic low VOL 0 5 V max IOL 10 mA max Logic high VOH 2 6 V min IIH 10 mA max Supported modes4 16 CH TTL DI and16 CH TTL DO 4 CH 32 bit general purpose timer counters Clock source Internal or External Ma...

Page 18: ...liant Dimension 120 mm x 87 mm I O connector 2 x 68 pin female VHDCI connectors Power requirement typical 5 VDC 1 2A 12 VDC 760 mA 12 VDC 50 mA Operating environment Ambient temperature 0 C to 45 C Re...

Page 19: ...t work at the same time Refer to section 4 3 and 4 4 5 Refer to Chapter 4 Input Range System Noise 10 V 0 78 LSBrms 5 V 0 80 LSBrms 2 5 V 0 98 LSBrms 2 V 0 96 LSBrms 1 25 V 0 77 LSBrms 1 V 0 81 LSBrms...

Page 20: ...rd must be protected from static discharge and physical shock Never remove any of the socketed parts except at a static free workstation Use the anti static bag shipped with the product to handle the...

Page 21: ...ver and SDK with a graphics driven interface for various application development environments DAQPilot comes as ADLINK s commitment to provide full support to its comprehensive line of data acquisitio...

Page 22: ...er is a smart device manager that opens up access to ADLINK data acquisition and test and mea surement products DAQMaster delivers all in one configura tions and provides you with a full support matri...

Page 23: ...supe rior performance and reliability from your data acquisition sys tem DASK kernel drivers now support the revolutionary Windows Vista OS Figure 1 4 Legacy Software Support Overview NOTE ADLINK stro...

Page 24: ...AMD64 and Intel x86 64 architectures X Digitally signed for Windows Vista 64 bit edition X Utilizes WOW64 subsystem to ensure that 32 bit applications run normally on 64 bit editions of Windows XP Win...

Page 25: ...I 9223 Layout 2 2 Connector Pin Assignment The PCI 9222 PCI 9223 card is equipped with two VHDCI 68 pin connectors CN1 is for analog input output while CN2 is for digital input output and encoder func...

Page 26: ...L5 AI6 AIH6 28 62 AI14 AIL6 AI7 AIH7 27 61 AI15 AIL7 AGND 26 60 AISENSE NC 25 59 NC NC 24 58 NC NC 23 57 NC NC 22 56 NC NC 21 55 NC NC 20 54 NC NC 19 53 NC NC 18 52 NC AGND 17 51 AGND AO0 16 50 AGND A...

Page 27: ...E AI8 AIH8 25 59 AI24 AIL8 AI9 AIH9 24 58 AI25 AIL9 AI10 AIH10 23 57 AI26 AIL10 AI11 AIH11 22 56 AI27 AIL11 AI12 AIH12 21 55 AI28 AIL12 AI13 AIH13 20 54 AI29 AIL13 AI14 AIH14 19 53 AI30 AIL14 AI15 AIH...

Page 28: ...GPI7 GPTC_AUX1 27 61 GPI15 GPTC_AUX3 DGND 26 60 DGND GPO0 GPTC_OUT0 25 59 GPO8 GPO1 GPTC_OUT1 24 58 GPO9 GPO2 GPTC_OUT2 23 57 GPO10 GPO3 GPTC_OUT3 22 56 GPO11 GPO4 21 55 GPO12 GPO5 20 54 GPO13 GPO6 1...

Page 29: ...pair marked as AIH 0 7 and AIL 0 7 PCI 9223 Analog Input Channels 0 31 Each channel pair AI i i 16 I 0 15 can be configured as either two single ended inputs or one differential input pair marked as A...

Page 30: ...ND Input GPTC 0 3 gate GPTC_OUT 0 3 DGND Output GPTC 0 3 output GPTC_UD 0 3 DGND Input GPTC 0 3 up down NC NC NC No connection Definition Pin Definition RESERVED 1 2 DGND SSI_ADCONV 3 4 DGND SSI_DAWR...

Page 31: ...ADCONV signal SSI_AD_TRIG Master Output Sends the internal AD_TRIG out Slave Input Accepts the SSI_AD_TRIG as the digital trigger signal SSI_DAWR Master Output Sends the DAWR out Slave Input Accepts t...

Page 32: ...ngle Ended RSE Non Referenced Single Ended NRSE and Differential Input DIFF Types of Signal Sources Floating Signal Sources A floating signal source means it is not connected in any way to the buildin...

Page 33: ...the grounding point The external analog input signal provides its own reference grounding point and is suitable for ground refer enced signals Referenced Single ended RSE Mode In referenced single end...

Page 34: ...and NRSE Input Connections Differential input mode The differential input mode provides two inputs that respond to signal voltage difference between them If the signal source is ground referenced the...

Page 35: ...equivalent source impedance If the source impedance is less than 100 ohms you can simply connect the negative side of the signal to AIGND as well as the negative input of the instrumentation amplifier...

Page 36: ...24 Hardware Information...

Page 37: ...care fully inspect the module for any damage Press down all socketed ICs to make sure that they are properly seated Do this only with the module placed on a firm flat surface WARNING Do not apply powe...

Page 38: ...by the system Configuration The card configuration is done on a card by card basis for all PCI cards on your system Because configuration is controlled by the system and the software there is no jumpe...

Page 39: ...end multiplexers all A D input channels are connected to one ADC ADI AD7685 7686 or equivalent As for the D A function 2 analog output channels are generated by one DAC chip TI DAC8812 The ADC DAC co...

Page 40: ...The A D acquisition is initiated by a trigger source and you must decide how to trigger the A D conversion The data acquisition will start once a trigger condition is matched After the end of an A D...

Page 41: ...ode Full scale Range 10V 5V 2 5V 2V Least significant bit 305 2uV 152 6uV 76 3uV 61 03uV FSR 1LSB 9 999695V 4 999847V 2 499924V 1 999938V 7FFF Midscale 1LSB 305 2uV 152 6uV 76 3uV 61 03uV 0001 Midscal...

Page 42: ...trigger an A D conversion The conversion clock of PCI 9222 PCI 9223 may come from three different clock sources internal hardware timer general purpose input channel GPI 0 GPI 7 or SSI system synchro...

Page 43: ...ition timing and the meaning of the four counters are illustrated in Figure 4 4 Timebase Clock Source In scan acquisition mode all A D conversions start on the output of counters which use Timebase as...

Page 44: ...SI_counter SI2_counter NumChan_counter Specifying Channels Gains and Input Configurations in the Channel Gain Queue The channel gain and input configurations can be specified in the Channel Gain Queu...

Page 45: ...ous scan data acquisition timing when a trigger event occurs Post Trigger Acquisition no retrigger Use post trigger acquisition in applications where you want to collect data after a trigger event The...

Page 46: ...g_no is set to 0 Figure 4 6 Post Trigger with Retrigger Gated Trigger Use the gated trigger acquisition function in applications where you want to collect data when trigger events are set to level hig...

Page 47: ...m memory with no host CPU intervention Bus mastering DMA provides the fastest data transfer rate on PCI bus Once the analog input operation starts control returns to your program The hardware temporar...

Page 48: ...n continuous memory blocks into a linked list allowing transfers of very large amounts of data without being limited by the fragment of small size memory You may configure the linked list for the inpu...

Page 49: ...e maximum DMA data transfer size is 2M double words 8 MB However by using chaining mode scatter gather there is no limitation for the DMA data transfer size You may also link the descriptor nodes circ...

Page 50: ...digital codes and output voltages Software Update This method is suitable for applications that need to generate D A output controlled by user programs In this mode the D A converter generates one ou...

Page 51: ...by the FPGA rather than by the application software Compare with the conventional software based waveform generation the precise hardware timing control guarantees non distorted waveform generation ev...

Page 52: ...gure 4 12 Counter Name Width Description Note UI_counter 32 bit Update Interval Defines the update interval between each data output Update Interval UI_counter Timebase UC_counter 32 bit Update Counts...

Page 53: ...orm Generation DLY2_counter 32 bit Defines the delay time to separate consecutive waveform generation This is applicable only in Iterative Waveform Generation mode Delay Time DLY2_counter Clock Timeba...

Page 54: ...13 Post Trigger Generation Delay Trigger Generation Use delay trigger when you want to delay the waveform generation after the trigger signal The delay time is determined by DLY1_counter as illustrate...

Page 55: ...acceptable trigger signals Refer to Figure 4 15 In this example two waveforms are generated after the first trigger signal The card then waits for another trigger signal When the next trigger signal i...

Page 56: ...isabled the waveform generation will not stop until a stop trigger is asserted An onboard data FIFO is used to buffer the waveform patterns for waveform generation If the size of a single waveform is...

Page 57: ...the UC_counter to 2 the generated waveform will be a 1 8 cycle sine wave for every waveform period and a complete sine wave will be generated for every 8 iterations If you specified a UC_counter value...

Page 58: ...pand the flexibility of iterative waveform generation DLY2_counter was implemented to separate consecutive waveform generations The DLY2_counter starts counting down right after a single waveform gene...

Page 59: ...and 5V TTL compliant TTL DI DO Programmable function I O can be used as static TTL compliant 8 CH digital input and 4 CH digital output You can read write these I O lines by software polling Its sampl...

Page 60: ...operation Basic Timer Counter Functions Each timer counter has three inputs that can be controlled via hardware or software applications They are clock input GPTC_CLK gate input GPTC_GATE and up down...

Page 61: ...t operating following a software start signal that is set by the software The GPTC software reset initializes the status of the counter and reloads the initial value to the counter The operation remai...

Page 62: ...e application Figure 4 19 illustrates the operation where initial count 0 count up mode Figure 4 19 Mode 2 Operation Mode 3 Single Pulse width Measurement The counter counts the pulse width of the sig...

Page 63: ...oftware start The two programmable parameters can be specified in terms of periods of the GPTC_CLK input by the software application GPTC_GATE is use to enable disable counting When GPTC_GATE is inact...

Page 64: ...strates the generation of a single pulse with a pulse delay of two and a pulse width of four Figure 4 22 Mode 5 Operation Mode 6 Re triggered Single Pulse Generation This mode is similar to Mode 5 exc...

Page 65: ...is executed again Figure 4 24 illustrates the generation of two pulses with a pulse delay of four and a pulse width of three Figure 4 24 Mode 7 Operation Mode 8 Continuous Gated Pulse Generation This...

Page 66: ...time period via the known clock frequency The maximum counting width is 32 bit Figure 4 26 illustrates how the counter value decreases in Edge Separation Measurement mode Figure 4 26 Mode 9 Operation...

Page 67: ...via DMA The GPI is a 16 bit data and the sample clock source can be configured from an internal timer pacer internal analog conversion clock or external clock When using an internal timer pacer as clo...

Page 68: ...d from the onboard timer pacer internal analog conversion clock or external clock When using the internal timer pacer as update clock source the GPO supports data update rates of up to 2MHz The intern...

Page 69: ...s position feedback The encoder sets are assigned in CN2 Encoder Isolation Input Module Figure 4 30 illustrates the encoder isolation phase A phase B and phase Z inputs module with 2500 Vrms protectio...

Page 70: ...When GPTC is set to CW CCW encoder mode and when the input EAx is connected to CW source signal and EBx is connected to CCW source signal pulses from EAx will cause the counter to counter up and spin...

Page 71: ...rature cycle and the increment and decrement of counter value in X1 encoder mode When phase A leads phase B the counter value increases on the first rising edge of CLK after phase A goes high When pha...

Page 72: ...l with phase A and B at a specific logic condition You must ensure that the logic level of phase Z is high during at least a portion of the phase you specify for reload when you use phase Z Otherwise...

Page 73: ...G2 ORG1 is used with phase Z With ORG enabled a high level on phase Z and ORG causes the counter to reload with a specified value in a specified phase of the quadrature cycle When you use ORG signal i...

Page 74: ...l Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the PCI 9222 PCI 9223 function I O You can set any DI line as e...

Page 75: ...values either from the original factory calibration or from a subsequently performed calibration Because of the fact that measurements and outputs errors may vary depending on time and temperature it...

Page 76: ...to the user configurable section of the EEPROM When auto calibration is completed you can save the new calibration constants to the user configurable banks in the EEPROM The date and the temperature w...

Page 77: ...party products not manufactured by ADLINK will be covered by the original manufactur ers warranty X For products containing storage devices hard drives flash cards etc please back up your data before...

Page 78: ...f battery fluid during or after change of batteries by customer user X Damage from improper repair by unauthorized ADLINK technicians X Products with altered and or damaged serial numbers are not enti...

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