ADLINK Technology NuDAQ PCI-9114DG, User Manual

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Registers Format
3.5 A/D Input Signal Range Control Register
The A/D range register is used to adjust the analog input ranges. This
register directly controls the PGA (programmable gain amplifi er).
When a different gain value is set, the analog input range will be
changed to its corresponding value.]
Address: BASE + 04h
Attribute:
write and read
Data Format:
Bit 7 6 5 4 3 2 1 0
BASE+04h X X X X X X G1 G0
BASE+05h X X X X X X X X
The relationship between gain setting and its corresponding A/D range
is listed in the table below.
G1 G0 Gain
HG/ DG
Analog Input Range
of PCI-9114HG
Analog Input Range
of PCI-9114DG
0 0 1 / 1
±
10V
±
10V
0 1 10 / 2
±
1V
±
5V
1 0 100 / 4
±
100 mV
±
2.5V
1 1 1000 / 8
±
10 mV
±
1.25V
3.6 A/D Status Read-back Register
The A/D FIFO status can be read back from this register.
Address: BASE + 0Ah
Attribute:
read only
Data Format:
Bit 7 6 5 4 3 2 1 0
BASE+0Ah X X X X AD_BUSY FF_FF FF_HF FF_EF
BASE+0Bh X X X X X X X X
FF_EF: ‘0’ means FIFO is empty
FF_HF: ‘0’ means FIFO is half-full
FF_FF: ‘0’ means FIFO is full, A/D data may have been loss
AD_BUSY: ‘0’ means AD is busy, the A/D data has not been latched in FIFO yet.
If AD_BUSY changes from ‘0’ to ‘1’, A/D data is written into FIFO.