ADLINK Technology COM Express Express-HLE User Manual Download

Page: 71 / 89

Express-HLE

Page 71

Feature

Options

Description

Trusted

Computing

Submenu

Intel TXT(LT) Configuration

Enabled

Disabled

Enables or Disables the High Precision Event Timer.

7.3.14.1

Miscellaneous > BIOS Security Configuration

Feature

Options

Description

SMI Lock

Enabled

Disabled

Enable or Disable the SMI Lock

BIOS Lock

Enabled

Disabled

Enable or Disable the BIOS lock enable (BLE) bit

GPIO Lock

Enabled

Disabled

Enable or Disable the GPIO lockdown

BIOS Interface Lock

Enabled

Disabled

Enable or Disable the BIOS interface lockdown

RTC RAM Lock

Enabled

Disabled

Enable or Disable bytes 38h-2Fh in the upper and lower 128-
byte bank of the RTC RAM lockdown

7.3.14.2

Miscellaneous > Trusted Computing

Feature

Options

Description

Security Device Support

Enabled

Disabled

Enables or Disables BIOS support for security device.
When disabled OS wil not show Security Device. TCG EFI
protocol and INT1A interface will not be available

Summary of Contents for COM Express Express-HLE

Page 1: ...Express HLE User s Manual Manual Revision 1 01 Revision Date October 22 2014 Part Number 50 1J050 1010...

Page 2: ...Page 2 Express HLE Revision History Revision Description Date By 1 00 Initial release 2014 04 23 JC 1 01 Add BIOS beep codes correct PCIe Configuration Switch settings 2014 10 22 JC...

Page 3: ...n if advised of the possibility of such damages Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the E...

Page 4: ...2 12 Environmental 9 2 13 Specification Compliance 9 2 14 Operating Systems 9 2 15 Function Diagram 10 2 16 Mechanical Drawing 11 3 Pinouts and Signal Descriptions 12 3 1 AB CD Pin Definitions 12 3 2...

Page 5: ...6 PCI Interrupt Routing Map 49 6 7 SMBus Slave Addresses 49 7 BIOS Setup 50 7 1 Menu Structure 50 7 2 Main 51 7 3 Advanced 56 7 4 Boot 72 7 5 Security 73 7 6 Save Exit 73 8 BIOS Checkpoints Beep Codes...

Page 6: ...port and DirectX Video Acceleration DXVA support for full AVC VC1 MPEG2 hardware decode Graphics outputs include VGA LVDS and three DDI ports supporting HDMI DVI DisplayPort The Express HLE is specifi...

Page 7: ...ansion Busses PCI Express x16 Gen3 or PCI Express 2 x8 or 1 x8 with 2 x4 6 PCI Express x1 AB Lanes 0 1 2 3 4 5 1 PCI Express x1 CD Lane 6 LPC bus SMBus system I2C user 2 3 Video Integrated in Processo...

Page 8: ...orts SATA 6Gb s SATA0 1 and 2 ports SATA 3Gb s SATA2 3 HM86 Serial 2 UART ports COM1 2 with console redirection GPIO 4 GPO and 4 GPI with interrupt 2 7 TPM Trusted Platform Module Chipset ATMEL AT97SC...

Page 9: ...60 C wide voltage input Extreme Rugged Operating Temperature 40 C to 85 C standard voltage input 2 12 Environmental Humidity 5 90 RH operating non condensing 5 95 RH storage and operating with confor...

Page 10: ...4 SPI 4x GPI Debug header 60 pin VGA PCIe x1 port 7 HD Audio UART1 UART0 DDC I2 C 1333 1600 MHz 1 8 GB DDR3L SPI_CS0 SPI_CS1 SPI_CS DDI 1 port B DP HDMI DVI SDVO DDI 2 port C DP HDMI DVI DDI 3 port D...

Page 11: ...Express HLE Page 11 2 16 Mechanical Drawing...

Page 12: ...B_CK C13 USB_SSRX3 D13 USB_SSTX3 A14 GBE0_CTREF B14 SMB_DAT C14 GND D14 GND A15 SUS_S3 B15 SMB_ALERT C15 DDI1_PAIR6 D15 DDI1_CTRLCLK_AUX A16 SATA0_TX B16 SATA1_TX C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_AUX...

Page 13: ...54 PEG_LANE_RV A55 PCIE_TX4 B55 PCIE_RX4 C55 PEG_RX1 D55 PEG_TX1 A56 PCIE_TX4 B56 PCIE_RX4 C56 PEG_RX1 D56 PEG_TX1 A57 GND B57 GPO2 C57 TYPE1 D57 TYPE2 A58 PCIE_TX3 B58 PCIE_RX3 C58 PEG_RX2 D58 PEG_TX...

Page 14: ...A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13 D94 PEG_TX13 A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13 D95 PEG_TX13 A96 TPM_PP B96 VGA_I2C_DAT C96 GND D96 GND A97 TYPE10 B97 SPI_CS C97 RSVD D97 RSVD A98 SER0_TX...

Page 15: ...tput 5V signal level I O 3 3V Bi directional signal 3 3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3Vsb Input 3 3V tolerant active in standby state P Power Input Output REF Reference vol...

Page 16: ...signed to drive a 37 5 Ohm equivalent load O Analog PD 150R Shall also be terminated on the carrier with 150 resistor to ground close to VGA connector VGA_GRN B91 Green for monitor Analog DAC output d...

Page 17: ...0_MDI1 GBE0_MDI2 GBE0_MDI2 GBE0_MDI3 GBE0_MDI3 A13 A12 A10 A9 A7 A6 A3 A2 Gigabit Ethernet Controller 0 Media Dependent Interface Differential Pairs 0 1 2 3 The MDI can operate in 1000 100 and 10Mbit...

Page 18: ...SATA1_RX B19 B20 Serial ATA channel 1 Receive Input differential pair I SATA AC coupled on Module SATA2_TX SATA2_TX A22 A23 Serial ATA channel 2 Transmit Output differential pair O SATA AC coupled on...

Page 19: ...Module PCIE_TX4 PCIE_TX4 A55 A56 PCI Express channel 4 Transmit Output differential pair O PCIE AC coupled on Module PCIE_RX4 PCIE_RX4 B55 B56 PCI Express channel 4 Receive Input differential pair I...

Page 20: ...USB over current sense USB ports 0 and 1 A pull up for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low I 3 3VSB P...

Page 21: ...Express HLE Page 21 3 3 10 USB Root Segmentation...

Page 22: ...watchdog time out event has occurred O 3 3V THRM B35 Input from off module temp sensor indicating an over temp situation I 3 3V THERMTRIP A35 Active low output indicating that the CPU has entered ther...

Page 23: ...purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI 1 A63 General purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI 2 A67 General purpose input...

Page 24: ...SUS_S4 A18 Indicates system is in Suspend to Disk state Active low output O 3 3VSB SUS_S5 A24 Indicates system is in Soft Off state O 3 3VSB WAKE0 B66 PCI Express wake up signal I 3 3VSB PU 10k 3 3VS...

Page 25: ...ath on USB2 I PCIE USB_SSTX2 USB_SSTX2 D9 D10 Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2 O PCIE AC coupled on Module USB_SSRX3 USB_SSRX3 C12 C13 Additional...

Page 26: ...splay Interface Hot Plug Detect I PCIE IF DDI1_DDC_AUX_SEL is floating I O PCIe DP1_AUX DDI1_CTRLCLK_AUX D15 IF DDI1_DDC_AUX_SEL pulled high I O OD 3 3V HDMI1_CTRLCLK IF DDI1_DDC_AUX_SEL is floating I...

Page 27: ...ir is used for the DP AUX signals If pulled high the AUX pair contains the CRTLCLK and CTRLDATA signals PD 1M DDI 3 Signal Pin Description I O PU PD Comment DDI3_PAIR0 DDI3_PAIR0 DDI3_PAIR1 DDI3_PAIR1...

Page 28: ...A_AUX DP1_AUX HMDI1_CTRLDATA D34 DDI1_DDC_AUX_SEL D39 DDI2_PAIR0 DP2_LANE0 TMDS2_DATA2 D40 DDI2_PAIR0 DP2_LANE0 TMDS2_DATA2 D42 DDI2_PAIR1 DP2_LANE1 TMDS2_DATA1 D43 DDI2_PAIR1 DP2_LANE1 TMDS2_DATA1 D4...

Page 29: ...C74 C75 C78 C79 C81 C82 C85 C86 C88 C89 C91 C92 C94 C95 C98 C99 C101 C102 PCI Express Graphics transmit differential pairs I PCIE AC coupled on Module PEG_TX0 PEG_TX0 PEG_TX1 PEG_TX1 PEG_TX2 PEG_TX2 P...

Page 30: ...e 5 no IDE no PCI GND NC NC Pinout Type 6 no IDE no PCI The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off e g deactivates the ATX_ON signal...

Page 31: ...apter describes connectors and pinouts LEDs and switches that are used on the module but are not included in the PICMG standard specification Connector and LED Locations CD AB FAN 4 pin FAN 40 pin Deb...

Page 32: ...Page 32 Express HLE 4 1 40 pin Debug Connector FPC Connector type FCI 59GF Flex 10042867 Pin orientation Express HLE and the Debug Module...

Page 33: ...am interface continued OCD0B Include a jumper to connect OCD0A via 1K0 pull up to 3 3V_BMC 9 GND 29 PWRBTN 10 BIOS_DIS0 30 SYS_RESET 11 RST 31 CB_RESET 12 CLK33_LPC 32 CB_PWROK 13 LPC_FRAME 33 SUS_S3...

Page 34: ...low LED2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up WD LED LED OFF Watchdog counting WD LED LED...

Page 35: ...A_B0 CFG 4 2 I O processor 28 OBSDATA_D0 CFG 12 2 I processor 29 OBSDATA_B1 CFG 5 2 I O processor 30 OBSDATA_D1 CFG 13 2 I processor 31 GND GND NA 32 GND GND NA 33 OBSDATA_B2 CFG 6 2 I O processor 34...

Page 36: ...up Defaults RESET Button To perform a hardware reset of BIOS default settings perform the following steps 1 Shut down the system 2 Press the BIOS Setup Defaults RESET Button continuously and boot up t...

Page 37: ...Express HLE Page 37 4 6 Express HLE Switch Settings 4 6 1 Switch Locations SW4 SW1 SW3...

Page 38: ...an be configured to PICMG and Failsafe modes using SW3 Pin 2 Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1 In PICMG mode a BIOS chip CANNOT be placed in...

Page 39: ...Express BASE6 Reference Carrier to support bifurbication of the CPU s PEG interface PCIe x16 The card reroutes the PCIe x16 to two x8 and allows testing of two independent PCIe add on cards with x8 x4...

Page 40: ...Power cycles counter Boot counter Counts the number of boot attempts Watchdog Timer Type II Set Reset Disable Watchdog Timer Features auto reload at power up System Restart Cause Power loss BIOS Fail...

Page 41: ...ain Current Function 5 1 2 Main Current The BMC of the Express HLE implements a current monitor The current can be read by calling the SEMA function Get Main Current The function returns four 16 bit v...

Page 42: ...not needed or supported Exception Code Error Message 0 NOERROR 2 NO_SUSCLK 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 BIOS_FAIL 7 RESET_FAIL 8 POWER_FAIL 9 LOW_VIN 11 P3V3_S 12 P1V05_S 13 P3V3_A 14 VDDQ 15...

Page 43: ...4GB 20MB 4GB 19MB 1 FEC00000 FECFFFFF 1 MB APIC Configuration Space 15MB 16MB F00000 FFFFFF 1 MB ISA Hole 1MB 15MB 100000 EFFFFF 14MB Main Memory 0K 1MB 00000 FFFFFF 1MB DOS Compatibility Memory 6 2...

Page 44: ...0 0B1 and 0B4 0BF Interrupt controller 2 8259 equivalent 0B2 and 0B3 APM control and status port respectively 0C0 0DF DMA controller 2 8237A 5 equivalent 0E0 0EF Available 0F0 Co processor error regis...

Page 45: ...guration address register 32 bit I O only CF9 Reset Control register 8 bit I O CFC CFF PCI configuration data register 580 Smbus base address for SB 1C00 GPIO Base Address for SB 1800 PM ACPI Base Add...

Page 46: ...A No 14 Primary IDE controller IRQ14 via SERIRQ PIRQ Note 1 15 Secondary IDE controller IRQ15 via SERIRQ PIRQ Note 1 Note 1 These IRQs can be used for PCI devices when onboard device is disabled APIC...

Page 47: ...oller Note 1 17 N A PCIE Port 0 1 2 3 4 5 6 P E G Root Port Note 1 18 N A PCIE Port 0 1 2 3 4 5 6 P E G Root Port SMBus Controller EHCI Controller 2 Note 1 19 N A PCIE Port 0 1 2 3 4 5 6 P E G Root Po...

Page 48: ...ler 00h 1Ch 00h Internal Intel ICH Express Root port 1 00h 1Ch 01h Internal Intel ICH Express Root port 2 00h 1Ch 02h Internal Intel ICH Express Root port 3 00h 1Ch 03h Internal Intel ICH Express Root...

Page 49: ...8 Int0 INTA 16 INTB 17 INTD 19 INTA 16 INTA 16 INTB 17 INTD 19 INTA 16 Int1 INTB 17 INTC 18 INTA 16 INTB 17 INTB 17 INTC 18 INTA 16 INTB 17 Int2 INTC 18 INTD 19 INTB 17 INTC 18 INTC 18 INTD 19 INTB 17...

Page 50: ...ult setting options are presented in bold and the function of each setting is described in the right hand column of the respective table Main Advanced Boot Security Save Exit System Information Proces...

Page 51: ...cription CPU Brand String Info only Display CPU Brand Name Frequency Info only Display CPU Frequency Processor ID Info only Display CPU ID Stepping Info only Display CPU Stepping Number of Processors...

Page 52: ...Read only Display SMC manufacturing date Last Repair Date Read only Display SMC last repair date MAC ID Read only Display SMC MAC ID 7 2 4 2 System Management Temperatures and Fan Speed Feature Optio...

Page 53: ...tion Runtime Statistics Info only Total Runtime Read only The returned value specifies the total time in minutes the system is running in S0 state Current Runtime Read only The returned value specifie...

Page 54: ...Backlight Bright 255 The value range starts by 0 and ends by 255 7 2 4 8 System Management Smart Fan Feature Options Description Smart Fan Info only CPU Smart FanTemperature Source CPU Sensor System...

Page 55: ...tem Date Weekday MM DD YYYY Requires the alpha numeric entry of the day of the week day of the month calendar month and all 4 digits of the year indicating the century and year Fri XX XX 20XX System T...

Page 56: ...lay cache info L1 Code Cache Info only Display cache info L2 Cache Info only Display cache info L3 Cache Inf o only Display cache info Limit CPUID Maximum Disabled Enabled When Enabled the processor w...

Page 57: ...n Info only Display CAS to RAS tRCDmin Row Precharge tRPmin Info only Display Row Precharge tRPmin Active to Precharge tRASmin Info only Display Active to Precharge tRASmin XMP Profile 1 Info only Dis...

Page 58: ...ary PCIE Internal Graphics Auto Disabled Enable Keep IGD enabled based on the setup options Aperture Size 128MB 256MB 512MB Select the Aperture Size DVMT Pre Allocated XXM Select DVMT 5 0 Pre Allocate...

Page 59: ...evice GT Power Management Control Info only GT Info Info only Display GT info of Intel Graphics RC6 Render Standby Enabled Disabled Check to enable render standby support GT OverClocking Support Enabl...

Page 60: ...nabled Disabled If enabled then only IRRT volumes can span internal and eSATA drives If disabled then any RAID volume can span internal and eSATA drives Smart Response Technology Enabled Disabled Enab...

Page 61: ...ons and setup USB3 0 Support Enabled Disabled Enable Disable USB3 0 XHCI Controller Support XHCI Hand off Enabled Disabled This is a workaround for OSes without XHCI hand off support The XHCI ownershi...

Page 62: ...bled Disabled Enable Disable integrated LAN to wake the system The Wake On LAN cannot be disabled if ME is on at Sx state AMT Configuration Info only Intel AMT Enabled Disabled Enable Disable Intel R...

Page 63: ...their own VGA color palette to access the video core s palette PERR Generation Disabled Enabled Enables or Disables PCI Device to Generate PERR SERR Generation Disabled Enabled Enables Disables PCI De...

Page 64: ...th other hardware after S3 resume PEG Configuration System Agent Submenu PCH PCIe Configuration Submenu 7 3 7 1 PCI and PCIe PEG Configuration System Agent Feature Options Description PEG Configuratio...

Page 65: ...Decode Disabled Enable Enable Disable PCI Express Subtractive Decode PCIE Ports 1 4 Configuration 4x1 Port 1X2 2X1 Port 2X2 Port 1X4 Port To configure PCI E Port 1 4 of PCH 4X1 Port 1 4 x1 and Port 8...

Page 66: ...ress Device If enabled it will take more time at POST time Extra Bus Reserved 0 Extra Bus Reserved 0 7 for bridges behind this Root Bridge Reseved Memory 10 Reserved Memory Range for this Root Bridge...

Page 67: ...tion of serial port Select an optimal setting for Super IO device N5104D Super IO Configuration Info only Serial Port 1 Configuration Serial Port Device Settings Change Settings Enabled Disabled IO 24...

Page 68: ...Auto Control Detection of the Azalia device Disabled Azalia will be unconditionally disabled Enabled Azalia will be unconditionally enabled Auto Azalia will be enabled if present disabled other Azali...

Page 69: ...s Recorder Mode Disabled Enable With this mode enabled only text will be sent This is to capture Terminal data Resolution 100x31 Disabled Enable Enables or disables extended terminal resolution Legacy...

Page 70: ...0C is the Plan Of Record POR for all Intel mobile processors Active Trip Point Disabled 40 C 50 C 60 C 70 C BMC Default This value controls the temperature of the ACPI Active Trip Point the point in w...

Page 71: ...lock enable BLE bit GPIO Lock Enabled Disabled Enable or Disable the GPIO lockdown BIOS Interface Lock Enabled Disabled Enable or Disable the BIOS interface lockdown RTC RAM Lock Enabled Disabled Ena...

Page 72: ...w disabling GA20 this option is useful when any RT code is executed above 1MB Option ROM Messages Force BIOS Keep Current Set display mode for Option ROM INT19 Trap Response Immediate Postponed BIOS r...

Page 73: ...users to change Image Execution policy and manage Secure Boot Keys 7 6 Save Exit 7 6 1 Reset Options Feature Options Description Save Changes and Reset Save changes and reset the system Save Changes...

Page 74: ...el Platform Innovation Framework for EFI the Framework The Framework refers the following boot phases which may apply to various status code checkpoint descriptions Security SEC initial low level init...

Page 75: ...Description 0x0 Not used Progress Codes 0x1 Power on Reset type detection soft hard 0x2 AP initialization before microcode loading 0x3 North Bridge initialization before microcode loading 0x4 South B...

Page 76: ...2C Memory initialization Memory presence detection 0x2D Memory initialization Programming memory timing information 0x2E Memory initialization Configuring memory 0x2F Memory initialization other 0x30...

Page 77: ...Progress Codes 0xE0 S3 Resume is stared S3 Resume PPI is called by the DXE IPL 0xE1 S3 Boot Script execution 0xE2 Video repost 0xE3 OS S3 wake vector call 0xE4 0xE7 Reserved for future AMI progress c...

Page 78: ...ule specific 0x68 PCI host bridge initialization 0x69 North Bridge DXE initialization is started 0x6A North Bridge DXE SMM initialization is started 0x6B North Bridge DXE initialization North Bridge m...

Page 79: ...Resources 0x96 PCI Bus Assign Resources 0x97 Console Output devices connect 0x98 Console input devices connect 0x99 Super IO Initialization 0x9A USB initialization is started 0x9B USB Reset 0x9C USB D...

Page 80: ...r 0xD3 Some of the Architectural Protocols are not available 0xD4 PCI resource allocation error Out of Resources 0xD5 No Space for Legacy Option ROM 0xD6 No Console Output Devices are found 0xD7 No Co...

Page 81: ...king up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xAC System has transitioned into ACPI mode Interrupt controller is in PIC mode 0xAA System has transitioned into ACPI...

Page 82: ...connector with 0 5mm for a stacking height of 5 mm This connector can be used with 5 mm through hole standoffs SMT type Tyco 3 6318491 6 Foxconn QT002206 4141 3H 220 pin board to board connector with...

Page 83: ...2 2 Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless depending on the thermal requirements 9 2 3 Installation Install a heat...

Page 84: ...ly onto the connectors on the carrier board as shown Then press down on the module until it is firmly seated on the carrier board Step 6 Use the five M2 5 L 16mm screws provided to secure the COM Expr...

Page 85: ...ition to the choice of 5 mm or 8mm board to board connectors there is the choice of Top and Bottom mounting In Top mounting the threaded standoffs are on the carrier board and the thermal solution is...

Page 86: ...threaded standoffs are DIP type and through hole standoffs are SMT type Other types not listed are available upon request 5mm through hole standoff SMT type P N 33 72000 0050 5mm threaded standoff DIP...

Page 87: ...avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high heat or high humidity Keep equipment properly ventilated do not block o...

Page 88: ...i Tech Park Pudong New Area Shanghai 201203 China Tel 86 21 5132 8988 Fax 86 21 5132 3588 Email market adlinktech com ADLINK Technology Beijing Address Rm 801 Power Creative E No 1 B D Shang Di East R...

Page 89: ...63 Email korea adlinktech com ADLINK Technology Singapore Pte Ltd Address 84 Genting Lane 07 02A Cityneon Design Centre Singapore 349584 Tel 65 6844 2261 Fax 65 6844 2263 Email singapore adlinktech co...

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