Express-BD7
Specifications
7
2.17. Functional Diagram
AB
Intel® Xeon® D
Pentium® D
“Broadwell
‐
DE”
LM73
Sensor
TPM 2.0
GP I2C
CD
SPI 0
BIOS
LPC bus
SODIMM 1
Up to 2400 MHz
4
‐
16 GB ECC/non
‐
ECC DDR4
16 PCIe lanes (Gen3)
(port 16
‐
31)
SPI
Debug
header
2x SATA 6Gb/s
(port 0/1)
4 x USB 2.0
(port 0/1/2/3)
4x USB 3.0 upgrade
(port 0/1/2/3)
UART0/1
SPI 1
BIOS
SODIMM 2
Up to 2400 MHz
4
‐
16 GB ECC/non
‐
ECC DDR4
1 PCIe lane (Gen2)
(port 6)
SPI_CS#
1x 10G KR
1x 10G KR
6 PCIe lanes (Gen2)
(port 0
‐
5)
New
SEMA
BMC
GPIO
PCA9535
4x GPO, 4x GPI
XDP
60
SMBus
LPC to UART
NCT5014D
GbE
Controller
1 PCIe lane (Gen2)
(port 7)
Note: Memory frequency dependent on SoC SKU
SMBus
NC
‐
SI
10G Sideband Signals
8 PCIe lanes (Gen3)
(port 8
‐
15)
Figure 1: Express-BD7 Functional Block Diagram
