28
Connector Pinouts on Module
4.4. XDP Debug Header
The debug port is a connection into a target-system environment that provides access to JTAG, run control, system
control, and observation resources. The XDP target system connector is a Samtec™ 60-pin BSH-030-01 series
connector.
Pin XDP Signal
Target Signal
I/O Device
Pin
XDP Signal
Target Signal
I/O
Device
1 GND
GND
NA
2 GND
GND
NA
3 OBSFN_A0 PREQ#
I/O Processor 4 OBSFN_C0
CFG[17]
2
I
Processor
5 OBSFN_A1 PRDY#
I/O Processor 6 OBSFN_C1
CFG[16]
2
I
Processor
7 GND
GND
NA
8 GND
GND
NA
9 OBSDATA_A0 CFG[0]
2
I/O
Processor
10
OBSDATA_C0
CFG[8]
2
I/O Processor
11 OBSDATA_A1 CFG[1]
2
I/O
Processor
12
OBSDATA_C1
CFG[9]
2
I/O Processor
13 GND
GND
NA
14 GND
GND
NA
15 OBSDATA_A2 CFG[2]
2
I/O
Processor
16
OBSDATA_C2
CFG[10]
2
I/O Processor
17 OBSDATA_A3 CFG[3]
2
I/O
Processor
18
OBSDATA_C3
CFG[11]
2
I/O Processor
19 GND
GND
NA
20 GND
GND
NA
21 OBSFN_B0
BPM#[0]
1
I/O
Processor
22
OBSFN_D0
CFG[19]
2
I/O Processor
23 OBSFN_B1
BPM#[1]
1
I/O
Processor
24
OBSFN_D1
CFG[18]
2
I/O Processor
25 GND
GND
NA
26 GND
GND
NA
27 OBSDATA_B0 CFG[4]
2
I/O
Processor
28
OBSDATA_D0
CFG[12]
2
I
Processor
29 OBSDATA_B1 CFG[5]
2
I/O
Processor
30
OBSDATA_D1
CFG[13]
2
I
Processor
31 GND
GND
NA
32 GND
GND
NA
33 OBSDATA_B2 CFG[6]
2
I/O
Processor
34
OBSDATA_D2
CFG[14]
2
I/O Processor
35 OBSDATA_B3 CFG[7]
2
I/O
Processor
36
OBSDATA_D3
CFG[15]
2
I/O Processor
37 GND
GND
NA
38 GND
GND
NA
39 HOOK0
PWRGOOD
I System
40 ITPCLK/HOOK4 Open
NA
41 HOOK11
BP_PWRGD_RST# O System
42 ITPCLK#/HOOK5 Open
NA
43 VCC_OBS_AB VCCIO_OUT
I System
44 VCC_OBS_CD VCCIO_OUT
I System
45 HOOK2
PWR_DEBUG
O Processor 46 HOOK6/RESET#
PLTRSTIN#
I System
47 HOOK3
PCH_SYS_PWROK O System
48
HOOK7/DBR# DBR#
O
System
49 GND
GND
NA
50 GND
GND
NA
51 SDA1
SDA
I/O System
52 TDO
TDO
I Processor
53 SCL1
SCL
I/O System
54 TRSTn
TRST#
O Processor
55 TCK1
Open
NA
56 TDI
TDI
O Processor
57 TCK0
TCK
O Processor 58 TMS
TMS
O Processor
59 GND
GND
NA
60 GND
GND
(or
XDP_PRESENT#
if required)
NA
Table 4: XDP Debug Header Pin Definition
Notes:
1. These signals are optional, can be left as OPEN/No-Connect if debug by Intel will not be needed.
2. These CFG signals can be left as Open/No Connect if not used as a strapping signal and top side probe
will be used to debug processor.
Refer to the "Shark Bay, Denlow and Broadwell U/Y Platforms Debug Port Design Guide", Document Number: 479493, Revision: 2.0
